AES/UNMASKED Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: `22488a4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	134.528us	1	1	100.00
V1	smoke	aes_smoke	6.000s	106.478us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	50.801us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	68.949us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.082ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	351.163us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	72.087us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	68.949us	20	20	100.00
		aes_csr_aliasing	7.000s	351.163us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	106.478us	50	50	100.00
		aes_config_error	6.000s	232.791us	50	50	100.00
		aes_stress	7.000s	569.211us	50	50	100.00
V2	key_length	aes_smoke	6.000s	106.478us	50	50	100.00
		aes_config_error	6.000s	232.791us	50	50	100.00
		aes_stress	7.000s	569.211us	50	50	100.00
V2	back2back	aes_stress	7.000s	569.211us	50	50	100.00
		aes_b2b	9.000s	133.055us	50	50	100.00
V2	backpressure	aes_stress	7.000s	569.211us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	106.478us	50	50	100.00
		aes_config_error	6.000s	232.791us	50	50	100.00
		aes_stress	7.000s	569.211us	50	50	100.00
		aes_alert_reset	8.000s	316.531us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	81.249us	50	50	100.00
		aes_config_error	6.000s	232.791us	50	50	100.00
		aes_alert_reset	8.000s	316.531us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	773.498us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	541.995us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	316.531us	50	50	100.00
V2	stress	aes_stress	7.000s	569.211us	50	50	100.00
V2	sideload	aes_stress	7.000s	569.211us	50	50	100.00
		aes_sideload	6.000s	145.989us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	188.436us	50	50	100.00
V2	stress_all	aes_stress_all	6.883m	10.037ms	9	10	90.00
V2	alert_test	aes_alert_test	5.000s	53.623us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	64.193us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	64.193us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	50.801us	5	5	100.00
		aes_csr_rw	6.000s	68.949us	20	20	100.00
		aes_csr_aliasing	7.000s	351.163us	5	5	100.00
		aes_same_csr_outstanding	6.000s	106.696us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	50.801us	5	5	100.00
		aes_csr_rw	6.000s	68.949us	20	20	100.00
		aes_csr_aliasing	7.000s	351.163us	5	5	100.00
		aes_same_csr_outstanding	6.000s	106.696us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	6.000s	69.079us	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	670.318us	49	50	98.00
		aes_control_fi	31.000s	10.002ms	282	300	94.00
		aes_cipher_fi	35.000s	10.005ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	83.740us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	83.740us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	83.740us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	83.740us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	77.282us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	23.000s	7.620ms	5	5	100.00
		aes_tl_intg_err	9.000s	247.187us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	247.187us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	316.531us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	83.740us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	106.478us	50	50	100.00
		aes_stress	7.000s	569.211us	50	50	100.00
		aes_alert_reset	8.000s	316.531us	50	50	100.00
		aes_core_fi	29.000s	10.012ms	61	70	87.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	83.740us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	65.451us	50	50	100.00
		aes_stress	7.000s	569.211us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	569.211us	50	50	100.00
		aes_sideload	6.000s	145.989us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	65.451us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	65.451us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	65.451us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	65.451us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	65.451us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	569.211us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	569.211us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	670.318us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	670.318us	49	50	98.00
		aes_control_fi	31.000s	10.002ms	282	300	94.00
		aes_cipher_fi	35.000s	10.005ms	323	350	92.29
		aes_ctr_fi	5.000s	50.722us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	670.318us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	670.318us	49	50	98.00
		aes_control_fi	31.000s	10.002ms	282	300	94.00
		aes_cipher_fi	35.000s	10.005ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	35.000s	10.005ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	670.318us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	670.318us	49	50	98.00
		aes_control_fi	31.000s	10.002ms	282	300	94.00
		aes_ctr_fi	5.000s	50.722us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	670.318us	49	50	98.00
		aes_control_fi	31.000s	10.002ms	282	300	94.00
		aes_cipher_fi	35.000s	10.005ms	323	350	92.29
		aes_ctr_fi	5.000s	50.722us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	316.531us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	670.318us	49	50	98.00
		aes_control_fi	31.000s	10.002ms	282	300	94.00
		aes_cipher_fi	35.000s	10.005ms	323	350	92.29
		aes_ctr_fi	5.000s	50.722us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	670.318us	49	50	98.00
		aes_control_fi	31.000s	10.002ms	282	300	94.00
		aes_cipher_fi	35.000s	10.005ms	323	350	92.29
		aes_ctr_fi	5.000s	50.722us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	670.318us	49	50	98.00
		aes_control_fi	31.000s	10.002ms	282	300	94.00
		aes_ctr_fi	5.000s	50.722us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	670.318us	49	50	98.00
		aes_control_fi	31.000s	10.002ms	282	300	94.00
		aes_cipher_fi	35.000s	10.005ms	323	350	92.29
V2S		TOTAL			930	985	94.42
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	14.000s	351.851us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1536	1602	95.88

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.33	97.67	94.75	98.80	93.63	98.07	93.33	98.85	97.59

Failure Buckets

Job timed out after * minutes has 21 failures:
- Test aes_control_fi has 7 failures.
  - 12.aes_control_fi.25706062192683656317324784626717878415342054190129263304522521860067151256298
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 59.aes_control_fi.65719505968866005994342560303218192079119771379124629860311202474621935069799
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/59.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 5 more failures.
- Test aes_cipher_fi has 14 failures.
  - 50.aes_cipher_fi.96956594911924506977796779965000912911627674456822228535037659465934802149250
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/50.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 115.aes_cipher_fi.90186325416274642611605669115624443957261105867144425317735900877239414129080
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/115.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 75.aes_cipher_fi.75089455087630488057060232727036835158252920011181162765020937169145062548962
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/75.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005489063 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005489063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 84.aes_cipher_fi.78017927299580095661673483396866482412706263367754429979902672019838743586884
    Line 136, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/84.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005633537 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005633537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 72.aes_control_fi.89992697307058510040027825611707314530162720018277524415885038663133504601279
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/72.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005290220 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005290220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 103.aes_control_fi.39821394720366673104169695752634591177354969838932910399957498292238853839602
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/103.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009465006 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009465006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.106649554260075629695368088588561022542249122639180066801505192503614012408472
Line 1116, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 351850633 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 351850633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.44569402677160667646198437040299612838755849042836531984229200565800333226263
Line 183, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  28755995 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  28755995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 7.aes_core_fi.94732520350474554373058032066924412641857858320117044420150501352885618441750
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021193432 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021193432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 14.aes_core_fi.43406693617717955367599317800653170436311976135873954949646285109697341505297
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10025507761 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025507761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 6.aes_core_fi.80911057347506039110459526331302177176444901592580060868555908146177092612514
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008862421 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008862421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 20.aes_core_fi.5284925046793239137693957163410259446803546942175062165501918133381895560066
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10023630713 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023630713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.95430997840510081694492751917328605162334388984935421331089542168239120748663
    Line 348, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1438678716 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1438678716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 4.aes_stress_all.54742792669305056960242094620063371713175385953123378959696058513514523046779
    Line 4803721, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 10037094016 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x294a1184, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
  UVM_INFO @ 10037094016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.85325928389979715202868293467396135726316214640376583044741592962045752894738
    Line 454, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2621050504 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2621050504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.92404557244883425162307706330686690453674365717720748678979744620284791045041
    Line 154, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  25859173 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  25859173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 37.aes_fi.97628068201502118134200615308447430468349288489599918747476801176438118278619
    Line 5649, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/37.aes_fi/latest/run.log
```
  UVM_FATAL @  21061045 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  21061045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```