CSRNG Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: `22488a4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	228.673us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	21.306us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	102.849us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	19.000s	541.103us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	270.349us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	37.306us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	102.849us	20	20	100.00
		csrng_csr_aliasing	9.000s	270.349us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	26.000s	1.514ms	198	200	99.00
V2	alerts	csrng_alert	1.333m	6.852ms	500	500	100.00
V2	err	csrng_err	11.000s	21.693us	500	500	100.00
V2	cmds	csrng_cmds	8.233m	37.399ms	50	50	100.00
V2	life cycle	csrng_cmds	8.233m	37.399ms	50	50	100.00
V2	stress_all	csrng_stress_all	24.683m	108.395ms	48	50	96.00
V2	intr_test	csrng_intr_test	6.000s	55.915us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	293.437us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	25.000s	1.940ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	25.000s	1.940ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	21.306us	5	5	100.00
		csrng_csr_rw	6.000s	102.849us	20	20	100.00
		csrng_csr_aliasing	9.000s	270.349us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	278.113us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	21.306us	5	5	100.00
		csrng_csr_rw	6.000s	102.849us	20	20	100.00
		csrng_csr_aliasing	9.000s	270.349us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	278.113us	20	20	100.00
V2		TOTAL			1436	1440	99.72
V2S	tl_intg_err	csrng_sec_cm	7.000s	118.652us	5	5	100.00
		csrng_tl_intg_err	14.000s	733.951us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	151.685us	50	50	100.00
		csrng_csr_rw	6.000s	102.849us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.333m	6.852ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	24.683m	108.395ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
		csrng_sec_cm	7.000s	118.652us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
		csrng_sec_cm	7.000s	118.652us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
		csrng_sec_cm	7.000s	118.652us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
		csrng_sec_cm	7.000s	118.652us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
		csrng_sec_cm	7.000s	118.652us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
		csrng_sec_cm	7.000s	118.652us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
		csrng_sec_cm	7.000s	118.652us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.333m	6.852ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	24.683m	108.395ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.333m	6.852ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	733.951us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
		csrng_sec_cm	7.000s	118.652us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
		csrng_sec_cm	7.000s	118.652us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	26.000s	1.514ms	198	200	99.00
		csrng_err	11.000s	21.693us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.200m	1.049ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1616	1630	99.14

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.77	98.66	96.74	100.00	97.48	92.08	100.00	97.36	90.25

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 0.csrng_stress_all_with_rand_reset.85429397463981786460261090877406722982732903763282935603966278222856733894870
    Line 109, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1048633356 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1048633356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.22558120721618599731532777649504777064971899581856379576260004357713469715551
    Line 104, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3619152639 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3619152639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:

Test csrng_stress_all has 2 failures.

22.csrng_stress_all.53910926734410033793927059766593016136955367812141203745842811907109501142700
Line 132, in log /nightly/runs/scratch/master/csrng-sim-xcelium/22.csrng_stress_all/latest/run.log

  UVM_ERROR @ 515957767 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 515957767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.csrng_stress_all.57334228879208864818227540303829360989657357464284035172671277900652257792669
Line 142, in log /nightly/runs/scratch/master/csrng-sim-xcelium/27.csrng_stress_all/latest/run.log

  UVM_ERROR @ 629704860 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 629704860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

Test csrng_intr has 2 failures.

106.csrng_intr.65840138274400442497044508375935284740287258414352655959183023112819938394848
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/106.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 185570087 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 185570087 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 185570087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

191.csrng_intr.71743269165125324633567894403769401263192665149727133525381500298586045123429
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/191.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 101109614 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 101109614 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 101109614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 9.csrng_stress_all_with_rand_reset.41686191076498049351448496952376790187555408236515249100862972241682025244133
    Line 107, in log /nightly/runs/scratch/master/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  14303144 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  14303144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```