DMA Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: 22488a4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	10.000s	1.456ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	12.000s	378.849us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	10.000s	3.476ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	28.660us	5	5	100.00
V1	csr_rw	dma_csr_rw	5.000s	13.638us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	16.000s	5.945ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	11.000s	1.112ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	70.874us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	13.638us	20	20	100.00
		dma_csr_aliasing	11.000s	1.112ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	2.067m	9.130ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	14.700m	286.720ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	27.967m	455.411ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	45.367m	271.815ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	14.700m	286.720ms	3	3	100.00
V2	dma_abort	dma_abort	20.000s	2.330ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	4.567m	74.410ms	3	3	100.00
V2	intr_test	dma_intr_test	5.000s	13.341us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	7.000s	50.226us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	7.000s	50.226us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	28.660us	5	5	100.00
		dma_csr_rw	5.000s	13.638us	20	20	100.00
		dma_csr_aliasing	11.000s	1.112ms	5	5	100.00
		dma_same_csr_outstanding	6.000s	136.257us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	28.660us	5	5	100.00
		dma_csr_rw	5.000s	13.638us	20	20	100.00
		dma_csr_aliasing	11.000s	1.112ms	5	5	100.00
		dma_same_csr_outstanding	6.000s	136.257us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	33.000s	1.453ms	5	5	100.00
		dma_generic_stress	45.367m	271.815ms	5	5	100.00
		dma_handshake_stress	14.700m	286.720ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	91.582us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.383m	61.614ms	5	5	100.00
		dma_longer_transfer	8.000s	281.373us	5	5	100.00
		TOTAL			304	304	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.71	96.97	95.19	96.93	95.97	82.72	82.76	97.77	41.35