EDN Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: 22488a4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	2.640s	20.101us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	2.550s	100.163us	5	5	100.00
V1	csr_rw	edn_csr_rw	2.650s	95.481us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.840s	467.418us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	2.820s	55.002us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	3.390s	137.234us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	2.650s	95.481us	20	20	100.00
		edn_csr_aliasing	2.820s	55.002us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.848m	9.103ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.848m	9.103ms	300	300	100.00
V2	genbits	edn_genbits	1.848m	9.103ms	300	300	100.00
V2	interrupts	edn_intr	2.850s	21.564us	50	50	100.00
V2	alerts	edn_alert	3.010s	35.587us	200	200	100.00
V2	errs	edn_err	2.970s	31.651us	100	100	100.00
V2	disable	edn_disable	2.510s	13.321us	50	50	100.00
		edn_disable_auto_req_mode	3.390s	52.880us	49	50	98.00
V2	stress_all	edn_stress_all	8.440s	361.774us	50	50	100.00
V2	intr_test	edn_intr_test	2.680s	13.773us	50	50	100.00
V2	alert_test	edn_alert_test	3.200s	63.577us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.890s	180.829us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.890s	180.829us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	2.550s	100.163us	5	5	100.00
		edn_csr_rw	2.650s	95.481us	20	20	100.00
		edn_csr_aliasing	2.820s	55.002us	5	5	100.00
		edn_same_csr_outstanding	2.940s	41.168us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	2.550s	100.163us	5	5	100.00
		edn_csr_rw	2.650s	95.481us	20	20	100.00
		edn_csr_aliasing	2.820s	55.002us	5	5	100.00
		edn_same_csr_outstanding	2.940s	41.168us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	18.760s	8.772ms	5	5	100.00
		edn_tl_intg_err	7.080s	408.014us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	2.540s	28.825us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	3.010s	35.587us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	18.760s	8.772ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	18.760s	8.772ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	18.760s	8.772ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	18.760s	8.772ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	3.010s	35.587us	200	200	100.00
		edn_sec_cm	18.760s	8.772ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	3.010s	35.587us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	7.080s	408.014us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.720h	10.000s	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1116	1130	98.76

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.65	98.32	94.23	97.07	90.70	96.33	99.78	93.13

Failure Buckets

• Job timed out after * minutes has 12 failures:
  • Test edn_stress_all_with_rand_reset has 12 failures.

    • 0.edn_stress_all_with_rand_reset.47785180559272578614534599128874585074466835788321518646394025689914691946702
      Log /nightly/runs/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 16.edn_stress_all_with_rand_reset.72063707135320913756935945897909051550397540341428860874574797746837777353395
      Log /nightly/runs/scratch/master/edn-sim-vcs/16.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 10 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 36.edn_stress_all_with_rand_reset.51753144264250612501185323239612418231242063513031606092979895529226821517893
      Line 355, in log /nightly/runs/scratch/master/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test edn_disable_auto_req_mode has 1 failures.

    • 44.edn_disable_auto_req_mode.107065663843228771466189918873333178302957310217626683866864000450965755905521
      Line 85, in log /nightly/runs/scratch/master/edn-sim-vcs/44.edn_disable_auto_req_mode/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---