HMAC Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: 22488a4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.050s	654.969us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.710s	89.974us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.580s	69.372us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	11.840s	2.109ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.050s	5.041ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.285m	198.183ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.580s	69.372us	20	20	100.00
		hmac_csr_aliasing	6.050s	5.041ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.429m	8.045ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.998m	18.792ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.889m	12.821ms	30	30	100.00
		hmac_test_sha384_vectors	9.704m	28.838ms	75	75	100.00
		hmac_test_sha512_vectors	8.756m	67.249ms	75	75	100.00
		hmac_test_hmac256_vectors	16.910s	1.976ms	50	50	100.00
		hmac_test_hmac384_vectors	19.880s	4.015ms	60	60	100.00
		hmac_test_hmac512_vectors	19.880s	1.484ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	51.720s	3.837ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	18.640m	40.499ms	10	10	100.00
V2	error	hmac_error	1.393m	19.115ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.735m	9.326ms	10	10	100.00
V2	save_and_restore	hmac_smoke	13.050s	654.969us	10	10	100.00
		hmac_long_msg	1.429m	8.045ms	10	10	100.00
		hmac_back_pressure	1.998m	18.792ms	25	25	100.00
		hmac_datapath_stress	18.640m	40.499ms	10	10	100.00
		hmac_burst_wr	51.720s	3.837ms	50	50	100.00
		hmac_stress_all	49.404m	40.866ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	13.050s	654.969us	10	10	100.00
		hmac_long_msg	1.429m	8.045ms	10	10	100.00
		hmac_back_pressure	1.998m	18.792ms	25	25	100.00
		hmac_datapath_stress	18.640m	40.499ms	10	10	100.00
		hmac_wipe_secret	1.735m	9.326ms	10	10	100.00
		hmac_test_sha256_vectors	3.889m	12.821ms	30	30	100.00
		hmac_test_sha384_vectors	9.704m	28.838ms	75	75	100.00
		hmac_test_sha512_vectors	8.756m	67.249ms	75	75	100.00
		hmac_test_hmac256_vectors	16.910s	1.976ms	50	50	100.00
		hmac_test_hmac384_vectors	19.880s	4.015ms	60	60	100.00
		hmac_test_hmac512_vectors	19.880s	1.484ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	13.050s	654.969us	10	10	100.00
		hmac_long_msg	1.429m	8.045ms	10	10	100.00
		hmac_back_pressure	1.998m	18.792ms	25	25	100.00
		hmac_datapath_stress	18.640m	40.499ms	10	10	100.00
		hmac_burst_wr	51.720s	3.837ms	50	50	100.00
		hmac_error	1.393m	19.115ms	10	10	100.00
		hmac_wipe_secret	1.735m	9.326ms	10	10	100.00
		hmac_test_sha256_vectors	3.889m	12.821ms	30	30	100.00
		hmac_test_sha384_vectors	9.704m	28.838ms	75	75	100.00
		hmac_test_sha512_vectors	8.756m	67.249ms	75	75	100.00
		hmac_test_hmac256_vectors	16.910s	1.976ms	50	50	100.00
		hmac_test_hmac384_vectors	19.880s	4.015ms	60	60	100.00
		hmac_test_hmac512_vectors	19.880s	1.484ms	75	75	100.00
		hmac_stress_all	49.404m	40.866ms	50	50	100.00
V2	stress_all	hmac_stress_all	49.404m	40.866ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.190s	14.919us	50	50	100.00
V2	intr_test	hmac_intr_test	2.380s	14.523us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.490s	81.020us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.490s	81.020us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.710s	89.974us	5	5	100.00
		hmac_csr_rw	2.580s	69.372us	20	20	100.00
		hmac_csr_aliasing	6.050s	5.041ms	5	5	100.00
		hmac_same_csr_outstanding	3.850s	173.555us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.710s	89.974us	5	5	100.00
		hmac_csr_rw	2.580s	69.372us	20	20	100.00
		hmac_csr_aliasing	6.050s	5.041ms	5	5	100.00
		hmac_same_csr_outstanding	3.850s	173.555us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.490s	111.485us	5	5	100.00
		hmac_tl_intg_err	5.450s	304.113us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.450s	304.113us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.050s	654.969us	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.510s	136.442us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	6.539m	24.805ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	3.120s	128.445us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.09	100.00	97.31	100.00	100.00	100.00	100.00	47.30