I2C Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: `22488a4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.593m	3.683ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	43.160s	1.262ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.260s	68.741us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.190s	33.670us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.840s	3.669ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.180s	43.271us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.550s	88.980us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.190s	33.670us	20	20	100.00
		i2c_csr_aliasing	3.180s	43.271us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	12.570s	633.998us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	47.894m	71.116ms	17	50	34.00
V2	host_maxperf	i2c_host_perf	24.337m	23.929ms	47	50	94.00
V2	host_override	i2c_host_override	2.300s	27.977us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.884m	31.243ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.395m	26.030ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.770s	143.454us	50	50	100.00
		i2c_host_fifo_fmt_empty	25.500s	854.130us	50	50	100.00
		i2c_host_fifo_reset_rx	13.660s	1.391ms	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.848m	3.121ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	45.140s	3.932ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	6.450s	698.631us	19	50	38.00
V2	target_glitch	i2c_target_glitch	16.000s	2.205ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	20.313m	68.395ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	9.050s	3.948ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.294m	32.151ms	50	50	100.00
		i2c_target_intr_smoke	10.750s	4.915ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.500s	276.026us	50	50	100.00
		i2c_target_fifo_reset_tx	3.290s	757.629us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	13.035m	56.748ms	50	50	100.00
		i2c_target_stress_rd	1.294m	32.151ms	50	50	100.00
		i2c_target_intr_stress_wr	4.778m	19.133ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	11.330s	11.088ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.982m	2.894ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	11.070s	4.785ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	42.220s	10.280ms	23	50	46.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.130s	5.922ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.160s	181.066us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	24.337m	23.929ms	47	50	94.00
		i2c_host_perf_precise	11.726m	24.382ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	45.140s	3.932ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	14.890s	1.462ms	45	50	90.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.180s	558.538us	50	50	100.00
		i2c_target_nack_acqfull_addr	4.800s	2.310ms	50	50	100.00
		i2c_target_nack_txstretch	3.340s	136.663us	37	50	74.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	25.390s	577.971us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.810s	4.024ms	50	50	100.00
V2	alert_test	i2c_alert_test	2.160s	32.248us	50	50	100.00
V2	intr_test	i2c_intr_test	2.230s	33.223us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.860s	741.733us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.860s	741.733us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.260s	68.741us	5	5	100.00
		i2c_csr_rw	2.190s	33.670us	20	20	100.00
		i2c_csr_aliasing	3.180s	43.271us	5	5	100.00
		i2c_same_csr_outstanding	2.530s	36.212us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.260s	68.741us	5	5	100.00
		i2c_csr_rw	2.190s	33.670us	20	20	100.00
		i2c_csr_aliasing	3.180s	43.271us	5	5	100.00
		i2c_same_csr_outstanding	2.530s	36.212us	20	20	100.00
V2		TOTAL			1674	1792	93.42
V2S	tl_intg_err	i2c_tl_intg_err	3.760s	150.715us	20	20	100.00
		i2c_sec_cm	2.720s	819.782us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.760s	150.715us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	37.510s	2.164ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.770s	798.255us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	47.730s	1.958ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1854	2042	90.79

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.87	97.13	89.82	74.17	71.43	94.04	98.52	89.96

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 36 failures:

Test i2c_host_stress_all has 25 failures.

0.i2c_host_stress_all.71249190351215452710578431330383215277228877867713033830226358125653927324160
Line 271, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 34619898466 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2035590

1.i2c_host_stress_all.25838379605420916365524473314908931684168263021201523603186901943927842539487
Line 266, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 43955610068 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2405080

... and 23 more failures.

Test i2c_host_mode_toggle has 11 failures.

2.i2c_host_mode_toggle.103583541849585807037488538209670036634299006898233917240765509479800676206918
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 472415681 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @28265

7.i2c_host_mode_toggle.45238416749207733339783422163478144695656326696904063312235636969833255269975
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 383696222 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @18137

... and 9 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
- Test i2c_target_unexp_stop has 32 failures.
  - 0.i2c_target_unexp_stop.103372436323306429770471714759238984872838182022511109508183017421100342780693
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 377801541 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 243 [0xf3])
  UVM_INFO @ 377801541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.101888000169878879683181546178687801897146311391928360395792063548059558949680
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 149760381 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 111 [0x6f])
  UVM_INFO @ 149760381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 30 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 27 failures:
- Test i2c_target_hrst has 27 failures.
  - 0.i2c_target_hrst.95958565666384592879653766419046319940864424787882135370818077631571589884292
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10092866157 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10092866157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_hrst.82677360634261869587201752199167474956994226503247343843650181273875294504422
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10089421203 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10089421203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 25 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.83942818527530777230868451057799551392904046181350430296128205308737356304038
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 610005546 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 610005546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.70998642874337182461591686562038068316354358199500459332222160120040861114774
Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1158040457 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1158040457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 10 failures.

0.i2c_target_stress_all_with_rand_reset.32905426753920885921780320596100742891693134087847969450322232494140815871422
Line 101, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 828545009 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 828545009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.84854743188925380591179563502290856795476518353976413984883615792577828621229
Line 101, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2559398660 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2559398660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 16 failures:

Test i2c_host_mode_toggle has 15 failures.

1.i2c_host_mode_toggle.92659306970675530882887528144948308138132046251042147725994886486948068837410
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 192983807 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

4.i2c_host_mode_toggle.25368859986973581266503282444916483087216756055146620049558085972674282045153
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 285004342 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 13 more failures.

Test i2c_host_perf has 1 failures.

25.i2c_host_perf.11137526681154165117396755458654985667474067564423410154935360159060431218095
Line 77, in log /nightly/runs/scratch/master/i2c-sim-vcs/25.i2c_host_perf/latest/run.log

  UVM_ERROR @ 2553951961 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 13 failures:
- Test i2c_target_nack_txstretch has 13 failures.
  - 0.i2c_target_nack_txstretch.45214697797387129858149800751002916923363923009423881606277977993540470377723
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 140218760 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 140218760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_nack_txstretch.24024973806278611768375079353177575012507766816385629159934985663053414518672
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 161716803 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 161716803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 13 failures:
- Test i2c_target_unexp_stop has 13 failures.
  - 3.i2c_target_unexp_stop.27690610429359900554932700637243142180262664406305809183621778657736888941361
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  96575572 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  96575572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_unexp_stop.95539047295070328077044779851266258295962986931699574996534362713813544293940
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 174144867 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 174144867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 6 failures:
- Test i2c_target_tx_stretch_ctrl has 5 failures.
  - 11.i2c_target_tx_stretch_ctrl.54512030641016245608890333713855074313554111223919938693654444467204811712384
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 14.i2c_target_tx_stretch_ctrl.57652839903507883014441519288050099364969998349960744331437246138714809647235
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 3 more failures.
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 36.i2c_target_fifo_watermarks_tx.49921221739078079288563617372661907817170691665763614970814111257776587892044
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:

Test i2c_target_unexp_stop has 5 failures.

1.i2c_target_unexp_stop.1915586933807570706360159737748588730419348380005859623288554305957864820851
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 176046933 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 176046933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.i2c_target_unexp_stop.23746246566332392492649196403111953200150914698878670025127723383616648235156
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @  66709539 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @  66709539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:

Test i2c_host_stress_all has 5 failures.

14.i2c_host_stress_all.96954231333858079725050405722997608859024518580484099112519130505487185593954
Line 171, in log /nightly/runs/scratch/master/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 30837814280 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2232030

16.i2c_host_stress_all.59653025902254338847708946247448676675588545584732340525135538483527478043284
Line 244, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 193461153381 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @5111220

... and 3 more failures.

UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
- Test i2c_host_mode_toggle has 4 failures.
  - 6.i2c_host_mode_toggle.4597208057885860026820103778192581604602137534263061938383258167666056305289
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 104615924 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xb304d514, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 104615924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.i2c_host_mode_toggle.62478706480531884611559989563173172148267371152693823230922550016553787035184
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 129016974 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x4d942394, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 129016974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
- Test i2c_target_stretch has 4 failures.
  - 13.i2c_target_stretch.111167120593021044831685642016844345573405887996104001427082894476298859522995
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10002332541 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10002332541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 34.i2c_target_stretch.1689445247387645285865813152068765601671883402762171113826015846619358070153
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/34.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10010751197 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10010751197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
Job timed out after * minutes has 2 failures:
- Test i2c_host_stress_all has 1 failures.
  - 3.i2c_host_stress_all.85885570307303218418893533316134140069715944266027461583335509376333997815852
    Log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_perf has 1 failures.
  - 24.i2c_host_perf.31832871626163007382646461763057246100026993554051747916373925430132514984980
    Log /nightly/runs/scratch/master/i2c-sim-vcs/24.i2c_host_perf/latest/run.log
```
  Job timed out after 60 minutes
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 0.i2c_host_mode_toggle.60448803687656478917220233004722800498667309407785841970155894598328205755654
    Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  ../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
- Test i2c_target_intr_stress_wr has 1 failures.
  - 3.i2c_target_intr_stress_wr.27381082121668269884052408501215813493611909188246850871878530806326634224954
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 19962297356 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 19962297356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=67) has 1 failures:
- Test i2c_host_perf has 1 failures.
  - 5.i2c_host_perf.67907066206261475501053112153597632703131251757855652538599470217326044206079
    Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_perf/latest/run.log
```
  UVM_FATAL @ 10406787041 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0x7f29e94, Comparison=CompareOpEq, exp_data=0x0, call_count=67)
  UVM_INFO @ 10406787041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 26.i2c_host_stress_all.48697764863007046694730570895595039112949200085084094927312052187815710020507
    Line 101, in log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 2747059478 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 44.i2c_host_stress_all.12170655626972638941366590717736827198843542753198367416561932006318490195501
    Line 196, in log /nightly/runs/scratch/master/i2c-sim-vcs/44.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```