KEYMGR Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: `22488a4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	40.830s	7.160ms	50	50	100.00
V1	random	keymgr_random	37.200s	1.707ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.640s	28.147us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.660s	17.969us	18	20	90.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.220s	499.851us	4	5	80.00
V1	csr_aliasing	keymgr_csr_aliasing	6.300s	1.092ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.470s	92.218us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.660s	17.969us	18	20	90.00
		keymgr_csr_aliasing	6.300s	1.092ms	4	5	80.00
V1		TOTAL			151	155	97.42
V2	cfgen_during_op	keymgr_cfg_regwen	1.753m	9.843ms	49	50	98.00
V2	sideload	keymgr_sideload	38.550s	4.650ms	50	50	100.00
		keymgr_sideload_kmac	54.330s	1.788ms	50	50	100.00
		keymgr_sideload_aes	37.390s	6.770ms	50	50	100.00
		keymgr_sideload_otbn	58.140s	3.283ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	30.250s	1.542ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.730s	2.363ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	15.930s	542.703us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	39.970s	2.002ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	31.340s	2.500ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	11.930s	2.193ms	50	50	100.00
V2	stress_all	keymgr_stress_all	2.658m	32.504ms	48	50	96.00
V2	intr_test	keymgr_intr_test	2.510s	28.375us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.530s	15.148us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.190s	667.671us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.190s	667.671us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.640s	28.147us	5	5	100.00
		keymgr_csr_rw	2.660s	17.969us	18	20	90.00
		keymgr_csr_aliasing	6.300s	1.092ms	4	5	80.00
		keymgr_same_csr_outstanding	4.060s	172.099us	14	20	70.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.640s	28.147us	5	5	100.00
		keymgr_csr_rw	2.660s	17.969us	18	20	90.00
		keymgr_csr_aliasing	6.300s	1.092ms	4	5	80.00
		keymgr_same_csr_outstanding	4.060s	172.099us	14	20	70.00
V2		TOTAL			730	740	98.65
V2S	sec_cm_additional_check	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
		keymgr_tl_intg_err	8.430s	827.668us	16	20	80.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.820s	215.832us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.820s	215.832us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.820s	215.832us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.820s	215.832us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	10.810s	240.745us	15	20	75.00
V2S	prim_count_check	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.430s	827.668us	16	20	80.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.820s	215.832us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.753m	9.843ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	37.200s	1.707ms	50	50	100.00
		keymgr_csr_rw	2.660s	17.969us	18	20	90.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	37.200s	1.707ms	50	50	100.00
		keymgr_csr_rw	2.660s	17.969us	18	20	90.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	37.200s	1.707ms	50	50	100.00
		keymgr_csr_rw	2.660s	17.969us	18	20	90.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.730s	2.363ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	31.340s	2.500ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	31.340s	2.500ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	37.200s	1.707ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	24.000s	2.941ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	15.230s	1.687ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.730s	2.363ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	15.230s	1.687ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	15.230s	1.687ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	15.230s	1.687ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	18.350s	724.938us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	15.230s	1.687ms	49	50	98.00
V2S		TOTAL			154	165	93.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	20.290s	522.080us	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1061	1110	95.59

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.10	98.11	98.32	100.00	99.01	98.63	91.23

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test keymgr_stress_all_with_rand_reset has 22 failures.
  - 0.keymgr_stress_all_with_rand_reset.23496398829562573307094366487771723555388612824603235817166165191450407347463
    Line 301, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 261099129 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 261099129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.keymgr_stress_all_with_rand_reset.87332503466085984539325621831090415475497490801148533049586767386583250654113
    Line 153, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 467057698 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 467057698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 19 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 5 failures.

1.keymgr_shadow_reg_errors_with_csr_rw.43867842690451129602225310538134803576501469916874996243691454776468406250542
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @ 101277566 ps: (keymgr_csr_assert_fpv.sv:429) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @ 101277566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_shadow_reg_errors_with_csr_rw.87042804685093874525309410042366286756656131836021949065689219695783989359179
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @  23167131 ps: (keymgr_csr_assert_fpv.sv:409) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @  23167131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_aliasing has 1 failures.

2.keymgr_csr_aliasing.23916835155283221634797960777213756312801045304802256782406177143296056811166
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @ 1092257204 ps: (keymgr_csr_assert_fpv.sv:424) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @ 1092257204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_same_csr_outstanding has 6 failures.

2.keymgr_same_csr_outstanding.21282008353208700078687417124792805716154408077871517962828028031587618931744
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @ 155849798 ps: (keymgr_csr_assert_fpv.sv:399) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @ 155849798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.keymgr_same_csr_outstanding.6162998182859001570065540952340106389524178410744255112115370284504280781124
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @ 630536882 ps: (keymgr_csr_assert_fpv.sv:394) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @ 630536882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_tl_intg_err has 4 failures.

3.keymgr_tl_intg_err.106196840230651179360027647613960965227670317929673720970977787686012791707283
Line 83, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @  10576577 ps: (keymgr_csr_assert_fpv.sv:399) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @  10576577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.keymgr_tl_intg_err.105159774806448590668565960518394897136014398775388956007581588558511531721505
Line 121, in log /nightly/runs/scratch/master/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @  80408143 ps: (keymgr_csr_assert_fpv.sv:434) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @  80408143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test keymgr_csr_bit_bash has 1 failures.

3.keymgr_csr_bit_bash.40755487158003409501241811568036709392426541964292002690802877841853907185189
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @ 868048107 ps: (keymgr_csr_assert_fpv.sv:469) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @ 868048107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.

UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:

Test keymgr_kmac_rsp_err has 1 failures.

4.keymgr_kmac_rsp_err.14991304711094027549057806627581940888440756431910070612419208632467596730637
Line 457, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  43131209 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  43131209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 1 failures.

4.keymgr_stress_all.43565276700233390856642079988271747796390030257878670042332861149463354943255
Line 1813, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 541177869 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 541177869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_custom_cm has 1 failures.

30.keymgr_custom_cm.94139388329326647201335850722165516544334580227733491547704796578849403423312
Line 124, in log /nightly/runs/scratch/master/keymgr-sim-vcs/30.keymgr_custom_cm/latest/run.log

  UVM_ERROR @   7006863 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   7006863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_cfg_regwen has 1 failures.

31.keymgr_cfg_regwen.60692972536327609886749631194467254892058895777648133425197529974498147959519
Line 151, in log /nightly/runs/scratch/master/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @  17089628 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  17089628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_protect has 1 failures.

32.keymgr_sideload_protect.87802047710614158917636100279377358630109249282087833993212998762930146128118
Line 128, in log /nightly/runs/scratch/master/keymgr-sim-vcs/32.keymgr_sideload_protect/latest/run.log

  UVM_ERROR @  19279279 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  19279279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:832) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:

Test keymgr_stress_all_with_rand_reset has 2 failures.

26.keymgr_stress_all_with_rand_reset.17007683197949805436116831691533666735385509316593934591862194172701880498523
Line 776, in log /nightly/runs/scratch/master/keymgr-sim-vcs/26.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1114062169 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1114062169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.keymgr_stress_all_with_rand_reset.31406770195271780268019429335203941635309800910816280344973962895536050680731
Line 97, in log /nightly/runs/scratch/master/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 423930746 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 423930746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerKey for Sealing Kmac has 1 failures:

Test keymgr_stress_all has 1 failures.

8.keymgr_stress_all.1399337715224271280456573147084847761177014441258031772747067579459359442839
Line 272, in log /nightly/runs/scratch/master/keymgr-sim-vcs/8.keymgr_stress_all/latest/run.log

  UVM_ERROR @  40725646 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10964042585261397781267143120995991342161586501831668425376605786396773584433608137211384532292979389427829071772854323791919483764287253666521443488695362 [0xd1571fb25f015fc863493839635f85711e20fac0cf15ebc71a9812b7918389efb0f8818dbeaeec7122972535efeb4f45f8975e0880b83a289d096e31a9870442] vs 10964042585261397781267143120995991342161586501831668425376605786396773584433608137211384532292979389427829071772854323791919483764287253666521443488695362 [0xd1571fb25f015fc863493839635f85711e20fac0cf15ebc71a9812b7918389efb0f8818dbeaeec7122972535efeb4f45f8975e0880b83a289d096e31a9870442]) KMAC key at state StOwnerKey for Sealing Kmac
  UVM_INFO @  40725646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---