KEYMGR_DPE Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: 22488a4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	2.336m	24.431ms	49	50	98.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	2.530s	39.119us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	2.460s	24.747us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	13.400s	1.404ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	8.250s	289.027us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	3.190s	31.281us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	2.460s	24.747us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.250s	289.027us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	intr_test	keymgr_dpe_intr_test	2.050s	39.103us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	2.620s	84.348us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	4.350s	827.449us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	4.350s	827.449us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	2.530s	39.119us	5	5	100.00
		keymgr_dpe_csr_rw	2.460s	24.747us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.250s	289.027us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.170s	203.479us	19	20	95.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	2.530s	39.119us	5	5	100.00
		keymgr_dpe_csr_rw	2.460s	24.747us	20	20	100.00
		keymgr_dpe_csr_aliasing	8.250s	289.027us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	3.170s	203.479us	19	20	95.00
V2		TOTAL			139	140	99.29
V2S	tl_intg_err	keymgr_dpe_sec_cm	9.720s	1.123ms	5	5	100.00
		keymgr_dpe_tl_intg_err	7.990s	181.595us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.820s	174.424us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.820s	174.424us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.820s	174.424us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.820s	174.424us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	7.710s	1.455ms	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	9.720s	1.123ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	9.720s	1.123ms	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			308	310	99.35

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.04	97.57	90.53	63.14	76.92	94.89	98.57	17.64

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:294) [keymgr_dpe_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:

  • Test keymgr_dpe_same_csr_outstanding has 1 failures.

    • 6.keymgr_dpe_same_csr_outstanding.32964202570809319592348109779444404529166049847357635356227157405184761783199
      Line 75, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/6.keymgr_dpe_same_csr_outstanding/latest/run.log

        UVM_ERROR @   5623840 ps: (cip_base_vseq.sv:294) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed masked_data == exp_data (256 [0x100] vs 0 [0x0]) addr 0x1e2e22d0 read out mismatch
        UVM_INFO @   5623840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_dpe_scoreboard.sv:565) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 1 failures:

  • Test keymgr_dpe_smoke has 1 failures.

    • 16.keymgr_dpe_smoke.32982471793553670912977725963439554193929086467188602291036811874423357726730
      Line 2320, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/16.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 1381984277 ps: (keymgr_dpe_scoreboard.sv:565) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h8460bb6faddcc2ec987cbd7b2d389a5f0a6aae14ebd468b99912ca1f7ceda0f3f2e1312838787ee47ca6880ac85e0daf63a167d013b1b8177f2fb7b8552ee3ce vs. act 'h0
        UVM_INFO @ 1381984277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---