KMAC/MASKED Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: `22488a4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.618m	4.416ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.700s	117.760us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.460s	47.774us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.850s	1.177ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.130s	735.307us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.060s	174.419us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.460s	47.774us	20	20	100.00
		kmac_csr_aliasing	10.130s	735.307us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.150s	27.621us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.920s	61.984us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.824m	2.684s	50	50	100.00
V2	burst_write	kmac_burst_write	24.436m	15.677ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.407m	327.442ms	5	5	100.00
		kmac_test_vectors_sha3_256	33.058m	120.984ms	5	5	100.00
		kmac_test_vectors_sha3_384	28.296m	47.347ms	5	5	100.00
		kmac_test_vectors_sha3_512	19.220m	35.251ms	5	5	100.00
		kmac_test_vectors_shake_128	29.080m	44.512ms	5	5	100.00
		kmac_test_vectors_shake_256	33.789m	211.892ms	5	5	100.00
		kmac_test_vectors_kmac	4.990s	247.124us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.610s	85.367us	5	5	100.00
V2	sideload	kmac_sideload	9.062m	103.815ms	50	50	100.00
V2	app	kmac_app	6.424m	5.917ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.904m	79.606ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.341m	14.424ms	50	50	100.00
V2	error	kmac_error	8.362m	151.672ms	50	50	100.00
V2	key_error	kmac_key_error	18.110s	6.915ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.040s	1.510ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.670s	7.341ms	19	20	95.00
V2	entropy_mode_error	kmac_entropy_mode_error	32.410s	5.855ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.458m	29.409ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.520s	847.714us	50	50	100.00
V2	stress_all	kmac_stress_all	42.764m	1.423s	50	50	100.00
V2	intr_test	kmac_intr_test	2.310s	45.618us	50	50	100.00
V2	alert_test	kmac_alert_test	2.320s	28.287us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.640s	184.991us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.640s	184.991us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.700s	117.760us	5	5	100.00
		kmac_csr_rw	2.460s	47.774us	20	20	100.00
		kmac_csr_aliasing	10.130s	735.307us	5	5	100.00
		kmac_same_csr_outstanding	4.370s	1.342ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.700s	117.760us	5	5	100.00
		kmac_csr_rw	2.460s	47.774us	20	20	100.00
		kmac_csr_aliasing	10.130s	735.307us	5	5	100.00
		kmac_same_csr_outstanding	4.370s	1.342ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.990s	126.975us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.990s	126.975us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.990s	126.975us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.990s	126.975us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.550s	184.505us	12	20	60.00
V2S	tl_intg_err	kmac_sec_cm	1.517m	17.058ms	5	5	100.00
		kmac_tl_intg_err	6.420s	294.248us	12	20	60.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.420s	294.248us	12	20	60.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.520s	847.714us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.618m	4.416ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.062m	103.815ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.990s	126.975us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.517m	17.058ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.517m	17.058ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.517m	17.058ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.618m	4.416ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.520s	847.714us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.517m	17.058ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.505m	14.209ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.618m	4.416ms	50	50	100.00
V2S		TOTAL			58	75	77.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.435m	13.282ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			918	940	97.66

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.14	99.09	94.47	99.89	78.17	97.09	99.37	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 16 failures:

Test kmac_tl_intg_err has 8 failures.

1.kmac_tl_intg_err.69942297496801503923414243993792776005316621524974054309960616717816274376504
Line 93, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  20500334 ps: (kmac_csr_assert_fpv.sv:515) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  20500334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_tl_intg_err.92553064720239595602563923789661451219617003240181090739841707702295615394508
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  11944783 ps: (kmac_csr_assert_fpv.sv:520) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  11944783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 8 failures.

3.kmac_shadow_reg_errors_with_csr_rw.101030080814020876633260988204878195563735352828967454736145111093658434070892
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  32654879 ps: (kmac_csr_assert_fpv.sv:535) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  32654879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.37312664631549849947422280728328047606736501888950418242091843684569698313997
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  13744036 ps: (kmac_csr_assert_fpv.sv:540) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  13744036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.100451531371104455754453439366204369492420232536700511773923341163751732754451
    Line 159, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6216902149 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6216902149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.10160275339254725162636133324640504682629946174154479322055564392797914436724
    Line 111, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 710756581 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 710756581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (kmac_edn_timeout_error_vseq.sv:68) [kmac_edn_timeout_error_vseq] Check failed cfg.m_kmac_app_agent_cfg[AppKeymgr].vif.kmac_data_rsp.error == * (* [*] vs * [*]) has 1 failures:
- Test kmac_edn_timeout_error has 1 failures.
  - 0.kmac_edn_timeout_error.83979649556514495846424550609507623036196997723634737155486932443327892562146
    Line 91, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest/run.log
```
  UVM_ERROR @ 1228567856 ps: (kmac_edn_timeout_error_vseq.sv:68) [uvm_test_top.env.virtual_sequencer.kmac_edn_timeout_error_vseq] Check failed cfg.m_kmac_app_agent_cfg[AppKeymgr].vif.kmac_data_rsp.error == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1228567856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_mubi has 1 failures.
  - 1.kmac_mubi.50593792468530973753591466651810576905946406409295571775625760954898604567428
    Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_mubi/latest/run.log
```
  UVM_ERROR @  42682772 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  42682772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```