KMAC/UNMASKED Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: `22488a4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.060m	34.182ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.630s	105.556us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.570s	103.319us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.520s	1.138ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.070s	963.706us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.470s	490.921us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.570s	103.319us	20	20	100.00
		kmac_csr_aliasing	11.070s	963.706us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.200s	32.117us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.050s	152.296us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.932m	132.016ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.453m	146.360ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	21.350m	35.106ms	5	5	100.00
		kmac_test_vectors_sha3_256	27.121m	78.880ms	5	5	100.00
		kmac_test_vectors_sha3_384	21.193m	307.468ms	5	5	100.00
		kmac_test_vectors_sha3_512	14.585m	124.877ms	5	5	100.00
		kmac_test_vectors_shake_128	25.154m	43.368ms	5	5	100.00
		kmac_test_vectors_shake_256	23.161m	34.331ms	5	5	100.00
		kmac_test_vectors_kmac	4.410s	1.154ms	5	5	100.00
		kmac_test_vectors_kmac_xof	4.220s	147.777us	5	5	100.00
V2	sideload	kmac_sideload	7.320m	88.878ms	50	50	100.00
V2	app	kmac_app	5.287m	31.926ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.811m	56.874ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.457m	299.587ms	50	50	100.00
V2	error	kmac_error	5.512m	53.206ms	50	50	100.00
V2	key_error	kmac_key_error	14.460s	1.916ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.100m	10.033ms	38	50	76.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.550s	959.400us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.050s	8.509ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	45.520s	12.710ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	29.130s	1.108ms	50	50	100.00
V2	stress_all	kmac_stress_all	30.270m	179.224ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.370s	19.734us	50	50	100.00
V2	alert_test	kmac_alert_test	2.310s	71.924us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.080s	272.431us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.080s	272.431us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.630s	105.556us	5	5	100.00
		kmac_csr_rw	2.570s	103.319us	20	20	100.00
		kmac_csr_aliasing	11.070s	963.706us	5	5	100.00
		kmac_same_csr_outstanding	3.770s	104.669us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.630s	105.556us	5	5	100.00
		kmac_csr_rw	2.570s	103.319us	20	20	100.00
		kmac_csr_aliasing	11.070s	963.706us	5	5	100.00
		kmac_same_csr_outstanding	3.770s	104.669us	20	20	100.00
V2		TOTAL			728	740	98.38
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.300s	131.850us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.300s	131.850us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.300s	131.850us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.300s	131.850us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.160s	843.366us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	1.254m	29.469ms	5	5	100.00
		kmac_tl_intg_err	5.960s	1.232ms	15	20	75.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.960s	1.232ms	15	20	75.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	29.130s	1.108ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.060m	34.182ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.320m	88.878ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.300s	131.850us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.254m	29.469ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.254m	29.469ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.254m	29.469ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.060m	34.182ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	29.130s	1.108ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.254m	29.469ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.546m	12.418ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.060m	34.182ms	50	50	100.00
V2S		TOTAL			63	75	84.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.793m	4.118ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			910	940	96.81

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.58	97.17	94.42	100.00	71.90	95.98	99.35	96.27

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_tl_intg_err has 5 failures.

0.kmac_tl_intg_err.94792056440041602080092780489244025015552418988463375012300177160328930028403
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  20112769 ps: (kmac_csr_assert_fpv.sv:535) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  20112769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_tl_intg_err.56602101571685878153181619684145455635230221855847901183650748760377850283453
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  20398679 ps: (kmac_csr_assert_fpv.sv:505) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  20398679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

2.kmac_shadow_reg_errors_with_csr_rw.81122010805820179314881848080592548750321648600210987546271608268621231316750
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  28856467 ps: (kmac_csr_assert_fpv.sv:495) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  28856467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_shadow_reg_errors_with_csr_rw.92348754314434737871640617162410608898667134248078753183866441972098014590689
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
  UVM_ERROR @ 141204901 ps: (kmac_csr_assert_fpv.sv:510) [ASSERT FAILED] prefix_3_rd_A
  UVM_INFO @ 141204901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.74356728165867791977268416451097012818005985363372155400275339398904987577169
    Line 150, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42269644068 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 42269644068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.107707470929042806433130403378835427915207669862768601416103547953865718681081
    Line 148, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17320346425 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 17320346425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 7.kmac_sideload_invalid.93856352016054003385855554616215106284022066623046634791064381217907512733895
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10087189364 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x573be000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10087189364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.kmac_sideload_invalid.50203951314083525232324785385083833650698231240013470085361037714563121731432
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10033342157 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x632c8000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10033342157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 3.kmac_stress_all_with_rand_reset.7449904364583184753404147144271308174236767463362819122012402606495658342094
    Line 89, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1033178735 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1033178735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=32) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 4.kmac_sideload_invalid.91283348778208618507672460641967654271164646712032471914385028115590633980315
    Line 106, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10202746250 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x41320000, Comparison=CompareOpEq, exp_data=0x1, call_count=32)
  UVM_INFO @ 10202746250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 18.kmac_sideload_invalid.45898931188741434933492685396704361362990264234521089833168365713430340164478
    Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10047200348 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6d595000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10047200348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 21.kmac_sideload_invalid.23245031788873526129487060081727134835555048706928155831012799488544994195000
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10162441185 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x913bb000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10162441185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 33.kmac_sideload_invalid.91726220375802041347949664968346050371159219603989657048486413179337290082233
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10018703883 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x48d10000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10018703883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 36.kmac_sideload_invalid.53884383274731242366792907043500893425894918657096889625202735806915968397288
    Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/36.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10365860975 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x997ce000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10365860975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 37.kmac_sideload_invalid.100894868600418023526709453643293053665419294038405322710670667987784761385758
    Line 95, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10615159397 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x47d7b000, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
  UVM_INFO @ 10615159397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 40.kmac_sideload_invalid.89247673349672838030853673714480824735119162066414710279410904985133800007200
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/40.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10450984069 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdd995000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
  UVM_INFO @ 10450984069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 41.kmac_sideload_invalid.91052896258873675546852101151538454810025307424589214366331758767820042018219
    Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/41.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10882296723 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe332000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10882296723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 47.kmac_sideload_invalid.65027463660424008415745108593435777419458755635442241991241396769260146004239
    Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/47.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10132223406 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xabb81000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10132223406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```