OTBN Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: `22488a4`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	51.000s	52.600us	1	1	100.00
V1	single_binary	otbn_single	1.117m	430.819us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	11.000s	33.257us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	78.319us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	100.696us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	23.425us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	37.433us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	78.319us	20	20	100.00
		otbn_csr_aliasing	8.000s	23.425us	5	5	100.00
V1	mem_walk	otbn_mem_walk	37.000s	3.624ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	1.854ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	56.000s	61.196us	10	10	100.00
V2	multi_error	otbn_multi_err	1.000m	611.735us	1	1	100.00
V2	back_to_back	otbn_multi	4.017m	2.369ms	10	10	100.00
V2	stress_all	otbn_stress_all	2.317m	894.490us	10	10	100.00
V2	lc_escalation	otbn_escalate	22.000s	53.530us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	12.000s	51.618us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	47.000s	632.139us	10	10	100.00
V2	alert_test	otbn_alert_test	12.000s	26.224us	50	50	100.00
V2	intr_test	otbn_intr_test	11.000s	29.302us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	239.266us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	239.266us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	11.000s	33.257us	5	5	100.00
		otbn_csr_rw	7.000s	78.319us	20	20	100.00
		otbn_csr_aliasing	8.000s	23.425us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	36.234us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	11.000s	33.257us	5	5	100.00
		otbn_csr_rw	7.000s	78.319us	20	20	100.00
		otbn_csr_aliasing	8.000s	23.425us	5	5	100.00
		otbn_same_csr_outstanding	12.000s	36.234us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	18.000s	37.518us	10	10	100.00
		otbn_dmem_err	18.000s	45.195us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	20.000s	181.585us	5	5	100.00
		otbn_controller_ispr_rdata_err	32.000s	74.117us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	45.120us	5	5	100.00
		otbn_urnd_err	13.000s	33.173us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	290.553us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	14.999us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	39.778us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
		otbn_tl_intg_err	28.000s	126.356us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	50.000s	217.512us	18	20	90.00
V2S	prim_fsm_check	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	51.000s	52.600us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	18.000s	45.195us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	18.000s	37.518us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	28.000s	126.356us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	22.000s	53.530us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	18.000s	37.518us	10	10	100.00
		otbn_dmem_err	18.000s	45.195us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	51.618us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	290.553us	5	5	100.00
		otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.117m	430.819us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	18.000s	37.518us	10	10	100.00
		otbn_dmem_err	18.000s	45.195us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	51.618us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	290.553us	5	5	100.00
		otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	22.000s	53.530us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	18.000s	37.518us	10	10	100.00
		otbn_dmem_err	18.000s	45.195us	15	15	100.00
		otbn_zero_state_err_urnd	12.000s	51.618us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	290.553us	5	5	100.00
		otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.117m	430.819us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	24.000s	396.258us	11	12	91.67
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	13.000s	24.182us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.033m	947.781us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.033m	947.781us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	22.000s	76.847us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	26.000s	114.174us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.050m	430.070us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.050m	430.070us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	18.000s	36.181us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.117m	430.819us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.117m	430.819us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.117m	430.819us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	4.017m	2.369ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.117m	430.819us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.117m	430.819us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	20.000s	126.841us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.117m	430.819us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.883m	4.421ms	3	5	60.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	5.900m	1.153ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			568	585	97.09

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.08	99.62	95.64	99.72	93.17	93.37	100.00	98.07	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test otbn_stress_all_with_rand_reset has 7 failures.
  - 0.otbn_stress_all_with_rand_reset.72403132942056910278423611588181642389314729006179212902316820746776063615743
    Line 169, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 926144033 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 926144033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.otbn_stress_all_with_rand_reset.333817187404439213753598415590084683745023916565365217498600614858263538727
    Line 235, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 936094017 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 936094017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_sec_wipe_err has 2 failures.

3.otbn_sec_wipe_err.61569488894337518510886480566426899780699017426682541734485408862931701782695
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 74157121 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  74157121 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  74157121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.otbn_sec_wipe_err.48363481955255948383902011278178545687858385314332744162876164038497299571343
Line 108, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 36181304 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  36181304 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  36181304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 2 failures.

43.otbn_escalate.61892495817064218951765020781554135376023157383746380349613776989463433367860
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/43.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 19170493 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  19170493 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  19170493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

56.otbn_escalate.114411289472198853650010919999534513521248970848229520607144069744298999378640
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/56.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 73633892 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  73633892 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  73633892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

0.otbn_sec_cm.85483328451420415969650254533158408318604671167745059632815265067662923171521
Line 127, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 92932422 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 92932422 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  92932422 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  92932422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_sec_cm.67531621311959053300956241440161381883665690900368206005733592533815335719492
Line 115, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 131211737 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 131211737 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @ 131211737 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @ 131211737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn_core.sv,969): Assertion OnlyWriteLoadDataBignumWhenDMemValid_A has failed has 1 failures:

Test otbn_ctrl_redun has 1 failures.

0.otbn_ctrl_redun.3322001872617374344562455896857701112342148917547500639540180031942349285573
Line 103, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,969): (time 54121170 PS) Assertion tb.dut.u_otbn_core.OnlyWriteLoadDataBignumWhenDMemValid_A has failed
  UVM_ERROR @  54121170 ps: (otbn_core.sv:969) [ASSERT FAILED] OnlyWriteLoadDataBignumWhenDMemValid_A
  UVM_INFO @  54121170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.59274010595708636157855128288326418056545785073158014669030826082775101058796
    Line 235, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1218407961 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1218407961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 16.otbn_passthru_mem_tl_intg_err.104435722480511702462228179013894357709276111653264325968811652989017983337492
    Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/16.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   3639603 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @   3639603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 19.otbn_passthru_mem_tl_intg_err.7782101024524922660151477504572261284954120912212384002164248866253645771549
    Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/19.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 154465095 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @ 154465095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```