ROM_CTRL/32KB Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: 22488a4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.060s	146.303us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	10.420s	189.280us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	9.320s	539.533us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.120s	168.998us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.840s	689.701us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.440s	176.195us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	9.320s	539.533us	20	20	100.00
		rom_ctrl_csr_aliasing	6.840s	689.701us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	8.750s	2.073ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.360s	167.239us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.450s	184.218us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	30.740s	578.135us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	12.720s	1.081ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	9.730s	553.896us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	13.230s	187.559us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	13.230s	187.559us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	10.420s	189.280us	5	5	100.00
		rom_ctrl_csr_rw	9.320s	539.533us	20	20	100.00
		rom_ctrl_csr_aliasing	6.840s	689.701us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.150s	180.742us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	10.420s	189.280us	5	5	100.00
		rom_ctrl_csr_rw	9.320s	539.533us	20	20	100.00
		rom_ctrl_csr_aliasing	6.840s	689.701us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.150s	180.742us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.034m	3.213ms	13	20	65.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	36.800s	1.618ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.279m	930.358us	5	5	100.00
		rom_ctrl_tl_intg_err	1.154m	1.764ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.279m	930.358us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.279m	930.358us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.034m	3.213ms	13	20	65.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.034m	3.213ms	13	20	65.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.034m	3.213ms	13	20	65.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.034m	3.213ms	13	20	65.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.034m	3.213ms	13	20	65.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.279m	930.358us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.279m	930.358us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.060s	146.303us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.060s	146.303us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.060s	146.303us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.154m	1.764ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.034m	3.213ms	13	20	65.00
		rom_ctrl_kmac_err_chk	12.720s	1.081ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.034m	3.213ms	13	20	65.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.034m	3.213ms	13	20	65.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.034m	3.213ms	13	20	65.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	36.800s	1.618ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.279m	930.358us	5	5	100.00
V2S		TOTAL			58	65	89.23
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	7.703m	5.218ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			259	266	97.37

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.67	100.00	99.41	100.00	100.00	100.00	98.97	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 7 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 7 failures.

    • 1.rom_ctrl_corrupt_sig_fatal_chk.21367318271138631234751646161725555244586859396210654903020460584525944704470
      Line 103, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 2549439819 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 2549439819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.rom_ctrl_corrupt_sig_fatal_chk.108228026534986908798819689104518685028259687341575556972384964130567079712283
      Line 75, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 4547446764 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 4547446764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.