RV_TIMER Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: 22488a4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.080s	56.464us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.020s	36.178us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.190s	28.452us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.220s	288.810us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.150s	61.107us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.960s	98.732us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.190s	28.452us	20	20	100.00
		rv_timer_csr_aliasing	2.150s	61.107us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	11.060s	12.896ms	20	20	100.00
V2	disabled	rv_timer_disabled	7.050s	2.622ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	9.815m	2.305s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	9.815m	2.305s	10	10	100.00
V2	stress	rv_timer_stress_all	17.050s	7.857ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.110s	24.237us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.180s	11.994us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.920s	190.454us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.920s	190.454us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.020s	36.178us	5	5	100.00
		rv_timer_csr_rw	2.190s	28.452us	20	20	100.00
		rv_timer_csr_aliasing	2.150s	61.107us	5	5	100.00
		rv_timer_same_csr_outstanding	2.380s	38.555us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.020s	36.178us	5	5	100.00
		rv_timer_csr_rw	2.190s	28.452us	20	20	100.00
		rv_timer_csr_aliasing	2.150s	61.107us	5	5	100.00
		rv_timer_same_csr_outstanding	2.380s	38.555us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.530s	1.133ms	5	5	100.00
		rv_timer_tl_intg_err	2.860s	164.563us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.860s	164.563us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.092m	29.517ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	2.040s	26.778us	10	10	100.00
		rv_timer_max	2.040s	51.037us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.95	100.00	100.00	100.00	--	100.00	100.00	99.71