SPI_DEVICE/1R1W Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: 22488a4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	11.686m	89.557ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.770s	25.128us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.710s	501.643us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.140s	24.525ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.120s	3.365ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.720s	59.567us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.710s	501.643us	20	20	100.00
		spi_device_csr_aliasing	15.120s	3.365ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.130s	13.122us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.920s	83.152us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.390s	22.546us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.350s	5.016us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.930s	6.970us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	7.520s	189.551us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.520s	189.551us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	32.030s	10.265ms	50	50	100.00
		spi_device_tpm_sts_read	2.700s	470.749us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	55.560s	10.483ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	34.210s	13.495ms	50	50	100.00
		spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	35.860s	14.079ms	50	50	100.00
		spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	35.860s	14.079ms	50	50	100.00
		spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	36.180s	4.125ms	50	50	100.00
		spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	36.180s	4.125ms	50	50	100.00
		spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	36.180s	4.125ms	50	50	100.00
		spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	36.180s	4.125ms	50	50	100.00
		spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	36.180s	4.125ms	50	50	100.00
		spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.100s	8.977ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.711m	14.510ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.711m	14.510ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.711m	14.510ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	58.270s	5.307ms	50	50	100.00
		spi_device_read_buffer_direct	22.710s	8.658ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.711m	14.510ms	50	50	100.00
		spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.228m	232.183ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	22.140s	2.653ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	22.140s	2.653ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	11.686m	89.557ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.538m	89.946ms	50	50	100.00
V2	stress_all	spi_device_stress_all	16.095m	228.186ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.380s	20.190us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.460s	45.006us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.360s	217.480us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.360s	217.480us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.770s	25.128us	5	5	100.00
		spi_device_csr_rw	3.710s	501.643us	20	20	100.00
		spi_device_csr_aliasing	15.120s	3.365ms	5	5	100.00
		spi_device_same_csr_outstanding	5.270s	949.733us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.770s	25.128us	5	5	100.00
		spi_device_csr_rw	3.710s	501.643us	20	20	100.00
		spi_device_csr_aliasing	15.120s	3.365ms	5	5	100.00
		spi_device_same_csr_outstanding	5.270s	949.733us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.450s	337.503us	5	5	100.00
		spi_device_tl_intg_err	18.660s	4.879ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.660s	4.879ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.446m	70.245ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.54	98.98	96.57	83.54	89.36	98.39	95.66	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.6519172074790901321328516274662824858102179884225246954996191663648835821486
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   6427367 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[66])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   6427367 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   6427367 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[962])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.23653649423890828544829974693187153247490679459984212700215569183883841447319
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1606819 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[36])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1606819 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1606819 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[932])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.34913158731226802852984005980928570809982405316512092998447755893300855543305
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4593528 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf1547b [111100010101010001111011] vs 0x0 [0])
        UVM_ERROR @   4640528 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe57408 [111001010111010000001000] vs 0x0 [0])
        UVM_ERROR @   4652528 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb7cbd6 [101101111100101111010110] vs 0x0 [0])
        UVM_ERROR @   4702528 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6e3877 [11011100011100001110111] vs 0x0 [0])
        UVM_ERROR @   4706528 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd24c45 [110100100100110001000101] vs 0x0 [0])