SPI_HOST Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: 22488a4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.067m	13.797ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	35.476us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	26.646us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	938.532us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	50.712us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	61.746us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	26.646us	20	20	100.00
		spi_host_csr_aliasing	5.000s	50.712us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	47.903us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	50.162us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	6.000s	74.642us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.767m	23.300ms	50	50	100.00
		spi_host_error_cmd	6.000s	20.532us	50	50	100.00
		spi_host_event	16.217m	132.634ms	50	50	100.00
V2	clock_rate	spi_host_speed	1.667m	200.000ms	49	50	98.00
V2	speed	spi_host_speed	1.667m	200.000ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	1.667m	200.000ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	10.817m	56.449ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	35.047us	50	50	100.00
V2	cpol_cpha	spi_host_speed	1.667m	200.000ms	49	50	98.00
V2	full_cycle	spi_host_speed	1.667m	200.000ms	49	50	98.00
V2	duplex	spi_host_smoke	2.067m	13.797ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.067m	13.797ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.967m	5.977ms	50	50	100.00
V2	spien	spi_host_spien	2.000m	7.408ms	49	50	98.00
V2	stall	spi_host_status_stall	7.717m	32.385ms	50	50	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	59.000s	8.210ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.767m	23.300ms	50	50	100.00
V2	alert_test	spi_host_alert_test	6.000s	15.427us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	16.423us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	147.051us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	147.051us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	35.476us	5	5	100.00
		spi_host_csr_rw	5.000s	26.646us	20	20	100.00
		spi_host_csr_aliasing	5.000s	50.712us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	92.970us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	35.476us	5	5	100.00
		spi_host_csr_rw	5.000s	26.646us	20	20	100.00
		spi_host_csr_aliasing	5.000s	50.712us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	92.970us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	317.707us	20	20	100.00
		spi_host_sec_cm	5.000s	41.364us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	317.707us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	10.950m	29.897ms	9	10	90.00
		TOTAL			837	840	99.64

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.30	96.83	93.37	98.69	94.47	88.02	100.00	97.27	90.42

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 8.spi_host_upper_range_clkdiv.43124974441496162711086705072520552442809189547168569336672791178578448473799
      Line 112, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test spi_host_speed has 1 failures.

    • 19.spi_host_speed.44982931616082389526114259124451207632631843505831261552032968007328037377483
      Line 126, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/19.spi_host_speed/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:234) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_spien has 1 failures.

    • 10.spi_host_spien.112299421025325917275587102084390654509983016351312578159002392064684892549546
      Line 346, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/10.spi_host_spien/latest/run.log

        UVM_FATAL @ 10482279129 ps: (spi_host_base_vseq.sv:234) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0xcb076794, Comparison=CompareOpEq, exp_data=0x0, call_count=56
        UVM_INFO @ 10482279129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---