SRAM_CTRL/MAIN Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: 22488a4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.433m	6.254ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.110s	20.624us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.200s	11.539us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.810s	1.066ms	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.280s	78.400us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.750s	1.820ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.200s	11.539us	20	20	100.00
		sram_ctrl_csr_aliasing	2.280s	78.400us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.649m	21.788ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.967m	24.193ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	19.777m	26.334ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.827m	8.407ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	36.426m	524.458ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.345m	142.116ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.239m	74.469ms	50	50	100.00
V2	executable	sram_ctrl_executable	24.340m	34.618ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.722m	1.062ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.148m	49.538ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.499m	3.186ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.582m	2.692ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.807m	6.087ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	24.090m	13.980ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.070s	6.679ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.290h	1.215s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.220s	21.144us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.900s	302.779us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.900s	302.779us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.110s	20.624us	5	5	100.00
		sram_ctrl_csr_rw	2.200s	11.539us	20	20	100.00
		sram_ctrl_csr_aliasing	2.280s	78.400us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.380s	327.313us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.110s	20.624us	5	5	100.00
		sram_ctrl_csr_rw	2.200s	11.539us	20	20	100.00
		sram_ctrl_csr_aliasing	2.280s	78.400us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.380s	327.313us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.172m	14.812ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.050s	2.489us	0	5	0.00
		sram_ctrl_tl_intg_err	4.360s	3.384ms	19	20	95.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.050s	2.489us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.360s	3.384ms	19	20	95.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	24.090m	13.980ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	24.090m	13.980ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.200s	11.539us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	24.340m	34.618ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	24.340m	34.618ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	24.340m	34.618ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.239m	74.469ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.100s	6.691ms	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.172m	14.812ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	13.290s	13.148ms	36	50	72.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.433m	6.254ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.433m	6.254ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	24.340m	34.618ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.050s	2.489us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.239m	74.469ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.050s	2.489us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.050s	2.489us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.433m	6.254ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.050s	2.489us	0	5	0.00
V2S		TOTAL			118	145	81.38
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	4.012m	12.596ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1163	1190	97.73

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.29	93.01	85.18	100.00	98.03	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 14 failures:

  • Test sram_ctrl_readback_err has 14 failures.

    • 2.sram_ctrl_readback_err.41446295728110637517275335077105195836061621658508595007438068678855667488440
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 660309417 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0xf) != exp (0xa)
        UVM_INFO @ 660309417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_readback_err.73981332730445733083811257483434135173886174893901448246976178071241495697147
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 13147695400 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x1f) != exp (0x76)
        UVM_INFO @ 13147695400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 12 more failures.

• Offending 'reqfifo_rvalid' has 7 failures:

  • Test sram_ctrl_mubi_enc_err has 7 failures.

    • 0.sram_ctrl_mubi_enc_err.58983396485821906719296721884932512829817606528707888381668285267950475657830
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1398417282 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1398417282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 12.sram_ctrl_mubi_enc_err.25265421868458523835149736320313413172563968449670098212974123419489384035563
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 673136550 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 673136550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 1.sram_ctrl_sec_cm.3103663274891569782027929002940629228895771313403912849134050581561620295739
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1619015 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1619015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.43476386922742690228838215349334449861170037693520973734584928557115215392743
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2489073 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2489073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.111574315435588655238920486476527133377086522437066091738645117480437750551035
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   3825418 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   3825418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.70666056888221195877453371749442353552714626277999447639263753644920539290
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   9995111 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   9995111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test sram_ctrl_tl_intg_err has 1 failures.

    • 6.sram_ctrl_tl_intg_err.32683931563396461335756073714427119114967613578201279872900591155772686011413
      Line 213, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_tl_intg_err/latest/run.log

        UVM_ERROR @  91017122 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @  91017122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---