SRAM_CTRL/RET Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: `22488a4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.770m	762.776us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.040s	24.460us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.130s	79.696us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.240s	155.404us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.160s	50.053us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.410s	137.409us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.130s	79.696us	20	20	100.00
		sram_ctrl_csr_aliasing	2.160s	50.053us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.810s	2.644ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.540s	684.700us	50	50	100.00
V1		TOTAL			204	205	99.51
V2	multiple_keys	sram_ctrl_multiple_keys	20.744m	21.443ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.486m	3.134ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.448m	13.831ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	19.702m	24.778ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.910s	2.953ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.217m	61.595ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.476m	426.329us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.906m	26.255ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.694m	1.092ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.805m	157.169us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.515m	1.329ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.696m	41.167ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.340s	28.673us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.307h	316.420ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.170s	143.587us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.860s	504.974us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.860s	504.974us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.040s	24.460us	5	5	100.00
		sram_ctrl_csr_rw	2.130s	79.696us	20	20	100.00
		sram_ctrl_csr_aliasing	2.160s	50.053us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.230s	24.787us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.040s	24.460us	5	5	100.00
		sram_ctrl_csr_rw	2.130s	79.696us	20	20	100.00
		sram_ctrl_csr_aliasing	2.160s	50.053us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.230s	24.787us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.810s	3.968ms	19	20	95.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.230s	5.680us	0	5	0.00
		sram_ctrl_tl_intg_err	3.540s	184.978us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.230s	5.680us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.540s	184.978us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.696m	41.167ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.696m	41.167ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.130s	79.696us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.217m	61.595ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.217m	61.595ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.217m	61.595ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.910s	2.953ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.840s	193.056us	48	50	96.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.810s	3.968ms	19	20	95.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.690s	52.113us	34	50	68.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.770m	762.776us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.770m	762.776us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.217m	61.595ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.230s	5.680us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.910s	2.953ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.230s	5.680us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.230s	5.680us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.770m	762.776us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.230s	5.680us	0	5	0.00
V2S		TOTAL			121	145	83.45
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.092m	1.405ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			1163	1190	97.73

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	99.26	93.01	85.10	100.00	97.99	98.58	98.14

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 15 failures:
- Test sram_ctrl_readback_err has 15 failures.
  - 8.sram_ctrl_readback_err.92508580424935721436895451460371887683819257928374744452290975022630730041494
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 116251955 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x7d) != exp (0x7e)
  UVM_INFO @ 116251955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.sram_ctrl_readback_err.104158853125003737626345472623126092038620629954885922685992543630228023816568
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  53728764 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x34) != exp (0x1c)
  UVM_INFO @  53728764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 13 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

0.sram_ctrl_sec_cm.74661905933189553415371090343448947347331270390550579033266021079538525188862
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   5680073 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   5680073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.sram_ctrl_sec_cm.47279592846018077320570559112648502554266416898958790627125694393924291655873
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   5986180 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   5986180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(rdata_o))' has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

1.sram_ctrl_sec_cm.58523759860556585910492625931433598138464143751926239523589411439529081441767
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   1551235 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1551235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sram_ctrl_sec_cm.25063690440250207278936751116482351953770809641189193806397237150569553333086
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   2716121 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2716121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending 'reqfifo_rvalid' has 2 failures:
- Test sram_ctrl_mubi_enc_err has 2 failures.
  - 4.sram_ctrl_mubi_enc_err.40510581948788258536109338613787671375099919031890349912636913002675624754184
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  25417209 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  25417209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 43.sram_ctrl_mubi_enc_err.30740102545180457501960559299323233282944223407265453227516406140268752994030
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/43.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  29819629 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  29819629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 2 failures.
  - 28.sram_ctrl_stress_all_with_rand_reset.56611723289060261445344877861220739543837566705812487898828447264664635223549
    Line 114, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/28.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6003662716 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6003662716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.sram_ctrl_stress_all_with_rand_reset.30625875414103324662079612826864126141571266169774301629411663362736669690773
    Line 154, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/38.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3714353033 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3714353033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(depth_o <= *'(Depth))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 2.sram_ctrl_sec_cm.3740169931425679481457148974301000034266335963172756594956710354243177314383
    Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   2764375 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   2764375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test sram_ctrl_passthru_mem_tl_intg_err has 1 failures.
  - 4.sram_ctrl_passthru_mem_tl_intg_err.54745878006691225247998204429564704959210502949789897092986387892304107340763
    Line 115, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 179455165 ps: uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer [uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 179455165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3295) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_readback_err has 1 failures.

5.sram_ctrl_readback_err.15965195624812030275955818872519760034187716654536194161173633742732024200674
Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

  UVM_ERROR @  49746610 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3295) { a_addr: 'h6bae4c30  a_data: 'h1e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h65  a_opcode: 'h0  a_user: 'h25d31  d_param: 'h0  d_source: 'h65  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  49746610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 8.sram_ctrl_csr_mem_rw_with_rand_reset.4852964684047155323374864802896337751270902214132384270255057431231739355945
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 157393554 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2 [0x2] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 157393554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```