UART Simulation Results

Friday May 23 2025 17:38:59 UTC

GitHub Revision: 22488a4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	21.170s	5.835ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.250s	29.682us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.390s	59.471us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.930s	60.084us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.380s	34.729us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.740s	81.804us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.390s	59.471us	20	20	100.00
		uart_csr_aliasing	2.380s	34.729us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.944m	95.850ms	50	50	100.00
V2	parity	uart_smoke	21.170s	5.835ms	50	50	100.00
		uart_tx_rx	2.944m	95.850ms	50	50	100.00
V2	parity_error	uart_intr	7.201m	354.071ms	50	50	100.00
		uart_rx_parity_err	5.652m	224.410ms	50	50	100.00
V2	watermark	uart_tx_rx	2.944m	95.850ms	50	50	100.00
		uart_intr	7.201m	354.071ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.575m	231.693ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.696m	138.020ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	13.115m	210.652ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.201m	354.071ms	50	50	100.00
V2	rx_break_err	uart_intr	7.201m	354.071ms	50	50	100.00
V2	rx_timeout	uart_intr	7.201m	354.071ms	50	50	100.00
V2	perf	uart_perf	21.950m	30.479ms	49	50	98.00
V2	sys_loopback	uart_loopback	36.130s	10.455ms	50	50	100.00
V2	line_loopback	uart_loopback	36.130s	10.455ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.486m	142.630ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.514m	37.471ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	47.000s	6.842ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.139m	7.033ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	19.514m	143.644ms	49	50	98.00
V2	stress_all	uart_stress_all	24.336m	377.579ms	49	50	98.00
V2	alert_test	uart_alert_test	2.180s	21.176us	50	50	100.00
V2	intr_test	uart_intr_test	2.360s	30.864us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.650s	482.311us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.650s	482.311us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.250s	29.682us	5	5	100.00
		uart_csr_rw	2.390s	59.471us	20	20	100.00
		uart_csr_aliasing	2.380s	34.729us	5	5	100.00
		uart_same_csr_outstanding	2.460s	18.836us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.250s	29.682us	5	5	100.00
		uart_csr_rw	2.390s	59.471us	20	20	100.00
		uart_csr_aliasing	2.380s	34.729us	5	5	100.00
		uart_same_csr_outstanding	2.460s	18.836us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	2.460s	561.045us	5	5	100.00
		uart_tl_intg_err	3.100s	166.357us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.100s	166.357us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.902m	7.682ms	100	100	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1317	1320	99.77

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.17	98.25	91.55	--	98.14	100.00	99.50

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 2 failures:

  • Test uart_perf has 1 failures.

    • 23.uart_perf.23888896228821645657608234761971822011127395584971311129256030111755486663018
      Line 74, in log /nightly/runs/scratch/master/uart-sim-vcs/23.uart_perf/latest/run.log

        UVM_ERROR @ 6227549177 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 6580127042 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 6/8
        UVM_INFO @ 6591585019 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 7/8
        UVM_INFO @ 6591876681 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 8/8
        UVM_INFO @ 6636605212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
      

  • Test uart_long_xfer_wo_dly has 1 failures.

    • 44.uart_long_xfer_wo_dly.114279696354569704201671305492369545475566781643303133041344305379953361216524
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/44.uart_long_xfer_wo_dly/latest/run.log

        UVM_ERROR @  11291711 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 34983041711 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/10
        UVM_INFO @ 41314916711 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/10
        UVM_INFO @ 70920166711 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/10
        UVM_INFO @ 87687916711 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 4/10
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_stress_all has 1 failures.

    • 34.uart_stress_all.66689599599675867471211958695572919656549937868159137724660069264165649413114
      Line 100, in log /nightly/runs/scratch/master/uart-sim-vcs/34.uart_stress_all/latest/run.log

        UVM_ERROR @ 131333891443 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
        UVM_INFO @ 134147561011 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 7/9
        UVM_INFO @ 150271042939 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 8/9
        UVM_ERROR @ 150837047467 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 151162579483 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1