AES/MASKED Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: `53e8d55`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	59.228us	1	1	100.00
V1	smoke	aes_smoke	11.000s	598.119us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	107.076us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	63.187us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	776.960us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	373.191us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	123.745us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	63.187us	20	20	100.00
		aes_csr_aliasing	6.000s	373.191us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	598.119us	50	50	100.00
		aes_config_error	8.000s	216.760us	50	50	100.00
		aes_stress	1.500m	4.915ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	598.119us	50	50	100.00
		aes_config_error	8.000s	216.760us	50	50	100.00
		aes_stress	1.500m	4.915ms	50	50	100.00
V2	back2back	aes_stress	1.500m	4.915ms	50	50	100.00
		aes_b2b	25.000s	815.858us	50	50	100.00
V2	backpressure	aes_stress	1.500m	4.915ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	598.119us	50	50	100.00
		aes_config_error	8.000s	216.760us	50	50	100.00
		aes_stress	1.500m	4.915ms	50	50	100.00
		aes_alert_reset	11.000s	493.005us	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	1.028ms	50	50	100.00
		aes_config_error	8.000s	216.760us	50	50	100.00
		aes_alert_reset	11.000s	493.005us	50	50	100.00
V2	trigger_clear_test	aes_clear	12.000s	649.359us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	346.188us	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	493.005us	50	50	100.00
V2	stress	aes_stress	1.500m	4.915ms	50	50	100.00
V2	sideload	aes_stress	1.500m	4.915ms	50	50	100.00
		aes_sideload	8.000s	116.261us	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	1.702ms	50	50	100.00
V2	stress_all	aes_stress_all	2.200m	15.117ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	85.734us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	808.798us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	808.798us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	107.076us	5	5	100.00
		aes_csr_rw	5.000s	63.187us	20	20	100.00
		aes_csr_aliasing	6.000s	373.191us	5	5	100.00
		aes_same_csr_outstanding	6.000s	287.639us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	107.076us	5	5	100.00
		aes_csr_rw	5.000s	63.187us	20	20	100.00
		aes_csr_aliasing	6.000s	373.191us	5	5	100.00
		aes_same_csr_outstanding	6.000s	287.639us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.567m	5.038ms	50	50	100.00
V2S	fault_inject	aes_fi	28.000s	3.371ms	50	50	100.00
		aes_control_fi	46.000s	10.146ms	272	300	90.67
		aes_cipher_fi	45.000s	10.008ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	126.779us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	126.779us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	126.779us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	126.779us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	716.929us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.573ms	5	5	100.00
		aes_tl_intg_err	6.000s	360.787us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	360.787us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	493.005us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	126.779us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	598.119us	50	50	100.00
		aes_stress	1.500m	4.915ms	50	50	100.00
		aes_alert_reset	11.000s	493.005us	50	50	100.00
		aes_core_fi	16.000s	10.013ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	126.779us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	89.208us	50	50	100.00
		aes_stress	1.500m	4.915ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.500m	4.915ms	50	50	100.00
		aes_sideload	8.000s	116.261us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	89.208us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	89.208us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	89.208us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	89.208us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	89.208us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.500m	4.915ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.500m	4.915ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	28.000s	3.371ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	28.000s	3.371ms	50	50	100.00
		aes_control_fi	46.000s	10.146ms	272	300	90.67
		aes_cipher_fi	45.000s	10.008ms	338	350	96.57
		aes_ctr_fi	7.000s	126.566us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	28.000s	3.371ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	28.000s	3.371ms	50	50	100.00
		aes_control_fi	46.000s	10.146ms	272	300	90.67
		aes_cipher_fi	45.000s	10.008ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	10.008ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	28.000s	3.371ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	28.000s	3.371ms	50	50	100.00
		aes_control_fi	46.000s	10.146ms	272	300	90.67
		aes_ctr_fi	7.000s	126.566us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	28.000s	3.371ms	50	50	100.00
		aes_control_fi	46.000s	10.146ms	272	300	90.67
		aes_cipher_fi	45.000s	10.008ms	338	350	96.57
		aes_ctr_fi	7.000s	126.566us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	493.005us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	28.000s	3.371ms	50	50	100.00
		aes_control_fi	46.000s	10.146ms	272	300	90.67
		aes_cipher_fi	45.000s	10.008ms	338	350	96.57
		aes_ctr_fi	7.000s	126.566us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	28.000s	3.371ms	50	50	100.00
		aes_control_fi	46.000s	10.146ms	272	300	90.67
		aes_cipher_fi	45.000s	10.008ms	338	350	96.57
		aes_ctr_fi	7.000s	126.566us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	28.000s	3.371ms	50	50	100.00
		aes_control_fi	46.000s	10.146ms	272	300	90.67
		aes_ctr_fi	7.000s	126.566us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	28.000s	3.371ms	50	50	100.00
		aes_control_fi	46.000s	10.146ms	272	300	90.67
		aes_cipher_fi	45.000s	10.008ms	338	350	96.57
V2S		TOTAL			943	985	95.74
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	26.000s	1.126ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1550	1602	96.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.41	98.63	96.52	99.44	95.66	98.07	97.78	98.96	98.79

Failure Buckets

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 18 failures:
- Test aes_control_fi has 18 failures.
  - 21.aes_control_fi.81906587954304966711418478510133952783462905074521997238211390330253899148739
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10145596176 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10145596176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.aes_control_fi.85652015314585763257177050606033316693592214696261231838422171130848010400457
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10044430278 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10044430278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
Job timed out after * minutes has 11 failures:
- Test aes_control_fi has 10 failures.
  - 16.aes_control_fi.65842011855748004729393509699384856483487805613234927723503749564239862710175
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 29.aes_control_fi.53645761906474488567086025099149189589690236026644404450935096601331023788121
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 1 failures.
  - 127.aes_cipher_fi.60658147309873557560591293576701221554399795805650580408256016239898289605789
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/127.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 42.aes_cipher_fi.3388093850172692399367869394997225396407632259107886442714764192308893903077
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012906915 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012906915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 56.aes_cipher_fi.10921839530736822207231782045754520081628040250336384338007076587959504890197
    Line 131, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/56.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002773674 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002773674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

2.aes_stress_all_with_rand_reset.45367702990403062719935891168128495475339755397343227653973497670464042112801
Line 804, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1586588678 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1586588678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.34481917046098265368914772208611455750186774135474964788019179399529584733919
Line 1033, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1126013338 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1126013338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.5164625795454860682232666496758984628009309176631365514273206448333303245382
    Line 213, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 991379521 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 991379521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.aes_stress_all_with_rand_reset.22088184933847104298687492894927665522507599744288250706115906905489184715172
    Line 613, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1278082450 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1278082450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:

Test aes_core_fi has 2 failures.

12.aes_core_fi.2568514303753363988632425159740366409055960309195580657981468009384373913111
Line 136, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/12.aes_core_fi/latest/run.log

  UVM_FATAL @ 10029205855 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029205855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

69.aes_core_fi.3496925861696911778392286581198645751379400071658027807597231122172858304488
Line 140, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/69.aes_core_fi/latest/run.log

  UVM_FATAL @ 10012656825 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012656825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.100219883911691006505069112382227201840670385684890857811728050977590956722435
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  47599471 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  47599471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.79306750228414207843980941512059807811674373387324589177715303869193097071319
    Line 153, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 124155014 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 124155014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.92832681234424557511007448621045123845187397054516129108377020183232366972659
    Line 660, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2749939064 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2749939064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```