AES/UNMASKED Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: `53e8d55`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	12.000s	130.236us	1	1	100.00
V1	smoke	aes_smoke	11.000s	56.812us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	104.503us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	69.992us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	869.500us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	655.255us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	145.455us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	69.992us	20	20	100.00
		aes_csr_aliasing	6.000s	655.255us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	56.812us	50	50	100.00
		aes_config_error	11.000s	116.380us	50	50	100.00
		aes_stress	11.000s	86.061us	50	50	100.00
V2	key_length	aes_smoke	11.000s	56.812us	50	50	100.00
		aes_config_error	11.000s	116.380us	50	50	100.00
		aes_stress	11.000s	86.061us	50	50	100.00
V2	back2back	aes_stress	11.000s	86.061us	50	50	100.00
		aes_b2b	14.000s	423.011us	50	50	100.00
V2	backpressure	aes_stress	11.000s	86.061us	50	50	100.00
V2	multi_message	aes_smoke	11.000s	56.812us	50	50	100.00
		aes_config_error	11.000s	116.380us	50	50	100.00
		aes_stress	11.000s	86.061us	50	50	100.00
		aes_alert_reset	11.000s	210.710us	50	50	100.00
V2	failure_test	aes_man_cfg_err	11.000s	57.734us	50	50	100.00
		aes_config_error	11.000s	116.380us	50	50	100.00
		aes_alert_reset	11.000s	210.710us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	298.189us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	253.585us	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	210.710us	50	50	100.00
V2	stress	aes_stress	11.000s	86.061us	50	50	100.00
V2	sideload	aes_stress	11.000s	86.061us	50	50	100.00
		aes_sideload	10.000s	65.257us	50	50	100.00
V2	deinitialization	aes_deinit	11.000s	158.359us	50	50	100.00
V2	stress_all	aes_stress_all	28.000s	10.962ms	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	71.470us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	487.317us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	487.317us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	104.503us	5	5	100.00
		aes_csr_rw	5.000s	69.992us	20	20	100.00
		aes_csr_aliasing	6.000s	655.255us	5	5	100.00
		aes_same_csr_outstanding	5.000s	281.462us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	104.503us	5	5	100.00
		aes_csr_rw	5.000s	69.992us	20	20	100.00
		aes_csr_aliasing	6.000s	655.255us	5	5	100.00
		aes_same_csr_outstanding	5.000s	281.462us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	9.000s	56.512us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	108.073us	50	50	100.00
		aes_control_fi	29.000s	10.005ms	280	300	93.33
		aes_cipher_fi	31.000s	10.002ms	320	350	91.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	103.264us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	103.264us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	103.264us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	103.264us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	212.981us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	413.377us	5	5	100.00
		aes_tl_intg_err	6.000s	180.518us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	180.518us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	210.710us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	103.264us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	56.812us	50	50	100.00
		aes_stress	11.000s	86.061us	50	50	100.00
		aes_alert_reset	11.000s	210.710us	50	50	100.00
		aes_core_fi	1.583m	10.043ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	103.264us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	53.595us	50	50	100.00
		aes_stress	11.000s	86.061us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	11.000s	86.061us	50	50	100.00
		aes_sideload	10.000s	65.257us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	53.595us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	53.595us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	53.595us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	53.595us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	53.595us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	11.000s	86.061us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	11.000s	86.061us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	108.073us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	108.073us	50	50	100.00
		aes_control_fi	29.000s	10.005ms	280	300	93.33
		aes_cipher_fi	31.000s	10.002ms	320	350	91.43
		aes_ctr_fi	8.000s	52.374us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	108.073us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	108.073us	50	50	100.00
		aes_control_fi	29.000s	10.005ms	280	300	93.33
		aes_cipher_fi	31.000s	10.002ms	320	350	91.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	31.000s	10.002ms	320	350	91.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	108.073us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	108.073us	50	50	100.00
		aes_control_fi	29.000s	10.005ms	280	300	93.33
		aes_ctr_fi	8.000s	52.374us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	108.073us	50	50	100.00
		aes_control_fi	29.000s	10.005ms	280	300	93.33
		aes_cipher_fi	31.000s	10.002ms	320	350	91.43
		aes_ctr_fi	8.000s	52.374us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	210.710us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	108.073us	50	50	100.00
		aes_control_fi	29.000s	10.005ms	280	300	93.33
		aes_cipher_fi	31.000s	10.002ms	320	350	91.43
		aes_ctr_fi	8.000s	52.374us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	108.073us	50	50	100.00
		aes_control_fi	29.000s	10.005ms	280	300	93.33
		aes_cipher_fi	31.000s	10.002ms	320	350	91.43
		aes_ctr_fi	8.000s	52.374us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	108.073us	50	50	100.00
		aes_control_fi	29.000s	10.005ms	280	300	93.33
		aes_ctr_fi	8.000s	52.374us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	108.073us	50	50	100.00
		aes_control_fi	29.000s	10.005ms	280	300	93.33
		aes_cipher_fi	31.000s	10.002ms	320	350	91.43
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.000s	1.769ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.36	97.73	94.88	98.84	93.66	98.07	93.33	98.65	97.38

Failure Buckets

Job timed out after * minutes has 29 failures:
- Test aes_ctr_fi has 1 failures.
  - 4.aes_ctr_fi.43125687608046847756860734840918311767776935556407437860726487321441155357756
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_control_fi has 11 failures.
  - 7.aes_control_fi.108431674475500465832320419502973798040157675779013922368883523474643465626497
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 22.aes_control_fi.16792179816186791314988836377915982050256457117586265464089094830416570637869
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 17 failures.
  - 42.aes_cipher_fi.101028518442217401159801488441506166073140142267548078541470698026415550522293
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 47.aes_cipher_fi.69913453314594250742689790787135025736179181832036833167863064314767049709851
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 15 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 20.aes_cipher_fi.55303629135869716676959342903760695916590034905215723253599875463174926757734
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012173534 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012173534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 24.aes_cipher_fi.100456745098988380933295762368081834046149714232844720938034541413220313615212
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014543536 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014543536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 72.aes_control_fi.58714051773975924441768555694233395909272367003313451662009410501247138557988
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/72.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010586119 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010586119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 85.aes_control_fi.28559270131668579621642174755514478988650701912912341566065335378464389469786
    Line 135, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/85.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005804011 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005804011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.8522701380531056577574483782689296939462773201559044295827361811879770410237
Line 189, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1164458782 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1164458782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.87352301176905122542317485385239699909525450170774082209219383903686976138526
Line 962, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 306822397 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 306822397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.63538904185550451162912052581382021553264862602635363552636141672620521011494
    Line 899, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1768572212 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1768572212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.aes_stress_all_with_rand_reset.13151615562086893357563022530392189547825036102082206376766202938314109966265
    Line 307, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 146591597 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 146591597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

7.aes_stress_all.38117012425293751236154749569217259436498589552716899667162477462004679277007
Line 69542, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 634069041 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 634045785 PS)
  UVM_ERROR @ 634069041 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 634069041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.4093108028650842474590076845934860261139317114707798118013354710826909046709
    Line 158, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 126888003 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 126888003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 19.aes_core_fi.91754582931703524224535349837770672763634914539037951065924805999797080710958
    Line 131, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10043227509 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xe9c70c84, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10043227509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```