CSRNG Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: `53e8d55`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	91.458us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	10.000s	102.463us	5	5	100.00
V1	csr_rw	csrng_csr_rw	7.000s	280.766us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	27.000s	1.581ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	268.416us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	246.482us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	7.000s	280.766us	20	20	100.00
		csrng_csr_aliasing	9.000s	268.416us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	26.000s	1.170ms	200	200	100.00
V2	alerts	csrng_alert	53.000s	3.028ms	500	500	100.00
V2	err	csrng_err	18.000s	20.094us	500	500	100.00
V2	cmds	csrng_cmds	19.467m	114.777ms	50	50	100.00
V2	life cycle	csrng_cmds	19.467m	114.777ms	50	50	100.00
V2	stress_all	csrng_stress_all	18.250m	58.491ms	47	50	94.00
V2	intr_test	csrng_intr_test	6.000s	155.760us	50	50	100.00
V2	alert_test	csrng_alert_test	11.000s	107.083us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	10.000s	223.786us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	10.000s	223.786us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	10.000s	102.463us	5	5	100.00
		csrng_csr_rw	7.000s	280.766us	20	20	100.00
		csrng_csr_aliasing	9.000s	268.416us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	149.898us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	10.000s	102.463us	5	5	100.00
		csrng_csr_rw	7.000s	280.766us	20	20	100.00
		csrng_csr_aliasing	9.000s	268.416us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	149.898us	20	20	100.00
V2		TOTAL			1437	1440	99.79
V2S	tl_intg_err	csrng_sec_cm	7.000s	138.831us	5	5	100.00
		csrng_tl_intg_err	14.000s	878.553us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	147.729us	50	50	100.00
		csrng_csr_rw	7.000s	280.766us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	53.000s	3.028ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	18.250m	58.491ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
		csrng_sec_cm	7.000s	138.831us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
		csrng_sec_cm	7.000s	138.831us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
		csrng_sec_cm	7.000s	138.831us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
		csrng_sec_cm	7.000s	138.831us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
		csrng_sec_cm	7.000s	138.831us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
		csrng_sec_cm	7.000s	138.831us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
		csrng_sec_cm	7.000s	138.831us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	53.000s	3.028ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	18.250m	58.491ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	53.000s	3.028ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	878.553us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
		csrng_sec_cm	7.000s	138.831us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
		csrng_sec_cm	7.000s	138.831us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	26.000s	1.170ms	200	200	100.00
		csrng_err	18.000s	20.094us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.417m	4.095ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1617	1630	99.20

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.70	98.61	96.62	99.94	97.30	92.08	100.00	97.36	90.04

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 0.csrng_stress_all_with_rand_reset.109888355289963448696615115529057345369517091772562846071139321032457579586865
    Line 100, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 503082698 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 503082698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.57912416754973190914048421013680915519675273885259998118686962540794695990004
    Line 100, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 257331080 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 257331080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq

has 3 failures:

Test csrng_stress_all has 3 failures.

24.csrng_stress_all.65647877383580992779443709963050626057972412065007844749774693459381728856797
Line 140, in log /nightly/runs/scratch/master/csrng-sim-xcelium/24.csrng_stress_all/latest/run.log

  UVM_ERROR @ 114838639 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 114838639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.csrng_stress_all.7376171884678532391492929524777486949065343068336978088219148935543598732290
Line 146, in log /nightly/runs/scratch/master/csrng-sim-xcelium/35.csrng_stress_all/latest/run.log

  UVM_ERROR @  67617511 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  67617511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 2.csrng_stress_all_with_rand_reset.63556920647444668738319556173310565247579682456556127799461197058676683762294
    Line 110, in log /nightly/runs/scratch/master/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  10335096 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  10335096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```