DMA Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	12.000s	442.150us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	11.000s	4.277ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	12.000s	900.769us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	60.059us	5	5	100.00
V1	csr_rw	dma_csr_rw	5.000s	25.012us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	15.000s	1.483ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	10.000s	152.959us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	31.229us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	25.012us	20	20	100.00
		dma_csr_aliasing	10.000s	152.959us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	2.083m	5.456ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	21.600m	198.211ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	31.033m	897.150ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	28.650m	273.637ms	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	21.600m	198.211ms	3	3	100.00
V2	dma_abort	dma_abort	24.000s	6.204ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	4.500m	77.498ms	3	3	100.00
V2	intr_test	dma_intr_test	5.000s	12.230us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	162.081us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	162.081us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	60.059us	5	5	100.00
		dma_csr_rw	5.000s	25.012us	20	20	100.00
		dma_csr_aliasing	10.000s	152.959us	5	5	100.00
		dma_same_csr_outstanding	6.000s	238.528us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	60.059us	5	5	100.00
		dma_csr_rw	5.000s	25.012us	20	20	100.00
		dma_csr_aliasing	10.000s	152.959us	5	5	100.00
		dma_same_csr_outstanding	6.000s	238.528us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	32.000s	487.972us	5	5	100.00
		dma_generic_stress	28.650m	273.637ms	5	5	100.00
		dma_handshake_stress	21.600m	198.211ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	390.274us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.833m	136.042ms	5	5	100.00
		dma_longer_transfer	31.000s	1.150ms	5	5	100.00
		TOTAL			304	304	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.56	96.89	95.05	96.20	95.97	82.72	82.76	97.77	41.46