EDN Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	2.580s	30.426us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	2.320s	25.406us	5	5	100.00
V1	csr_rw	edn_csr_rw	2.480s	15.458us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.280s	176.264us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	3.120s	80.010us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.760s	47.603us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	2.480s	15.458us	20	20	100.00
		edn_csr_aliasing	3.120s	80.010us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	50.350s	2.236ms	300	300	100.00
V2	csrng_commands	edn_genbits	50.350s	2.236ms	300	300	100.00
V2	genbits	edn_genbits	50.350s	2.236ms	300	300	100.00
V2	interrupts	edn_intr	2.750s	21.937us	50	50	100.00
V2	alerts	edn_alert	2.910s	29.308us	200	200	100.00
V2	errs	edn_err	2.930s	300.639us	100	100	100.00
V2	disable	edn_disable	2.450s	14.627us	50	50	100.00
		edn_disable_auto_req_mode	2.870s	66.256us	49	50	98.00
V2	stress_all	edn_stress_all	6.910s	360.425us	50	50	100.00
V2	intr_test	edn_intr_test	2.470s	15.695us	50	50	100.00
V2	alert_test	edn_alert_test	3.120s	72.392us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.140s	309.644us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.140s	309.644us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	2.320s	25.406us	5	5	100.00
		edn_csr_rw	2.480s	15.458us	20	20	100.00
		edn_csr_aliasing	3.120s	80.010us	5	5	100.00
		edn_same_csr_outstanding	2.750s	33.125us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	2.320s	25.406us	5	5	100.00
		edn_csr_rw	2.480s	15.458us	20	20	100.00
		edn_csr_aliasing	3.120s	80.010us	5	5	100.00
		edn_same_csr_outstanding	2.750s	33.125us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	11.620s	692.712us	5	5	100.00
		edn_tl_intg_err	4.360s	123.697us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	2.270s	14.444us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	2.910s	29.308us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	11.620s	692.712us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	11.620s	692.712us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	11.620s	692.712us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	11.620s	692.712us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.910s	29.308us	200	200	100.00
		edn_sec_cm	11.620s	692.712us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.910s	29.308us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.360s	123.697us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.893h	10.000s	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1108	1130	98.05

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.90	98.87	94.23	97.07	91.86	96.33	99.78	93.13

Failure Buckets

• Job timed out after * minutes has 20 failures:
  • Test edn_stress_all_with_rand_reset has 20 failures.

    • 3.edn_stress_all_with_rand_reset.21813405123111524161476511587182682887198550059598957790951102989702265097270
      Log /nightly/runs/scratch/master/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 6.edn_stress_all_with_rand_reset.39911917097010138820091828335656692900562416671199164726773993758612460554603
      Log /nightly/runs/scratch/master/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 18 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 0.edn_stress_all_with_rand_reset.20835565762030036727520467464343105924335540621010048715453695956724166160274
      Line 221, in log /nightly/runs/scratch/master/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test edn_disable_auto_req_mode has 1 failures.

    • 20.edn_disable_auto_req_mode.42359762306752650607267161115544363337661905732935068586518764299129025784237
      Line 85, in log /nightly/runs/scratch/master/edn-sim-vcs/20.edn_disable_auto_req_mode/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---