HMAC Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.990s	1.571ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.350s	148.418us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.440s	36.694us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.270s	1.110ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	7.160s	306.051us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	23.490m	724.303ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.440s	36.694us	20	20	100.00
		hmac_csr_aliasing	7.160s	306.051us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.956m	6.436ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.460m	1.853ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.322m	123.701ms	30	30	100.00
		hmac_test_sha384_vectors	10.386m	59.890ms	75	75	100.00
		hmac_test_sha512_vectors	9.456m	13.403ms	75	75	100.00
		hmac_test_hmac256_vectors	15.960s	1.335ms	50	50	100.00
		hmac_test_hmac384_vectors	18.580s	2.008ms	60	60	100.00
		hmac_test_hmac512_vectors	20.490s	390.899us	75	75	100.00
V2	burst_wr	hmac_burst_wr	50.440s	5.915ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	10.613m	23.766ms	10	10	100.00
V2	error	hmac_error	1.613m	12.269ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.947m	36.945ms	10	10	100.00
V2	save_and_restore	hmac_smoke	15.990s	1.571ms	10	10	100.00
		hmac_long_msg	1.956m	6.436ms	10	10	100.00
		hmac_back_pressure	1.460m	1.853ms	25	25	100.00
		hmac_datapath_stress	10.613m	23.766ms	10	10	100.00
		hmac_burst_wr	50.440s	5.915ms	50	50	100.00
		hmac_stress_all	26.317m	236.088ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.990s	1.571ms	10	10	100.00
		hmac_long_msg	1.956m	6.436ms	10	10	100.00
		hmac_back_pressure	1.460m	1.853ms	25	25	100.00
		hmac_datapath_stress	10.613m	23.766ms	10	10	100.00
		hmac_wipe_secret	1.947m	36.945ms	10	10	100.00
		hmac_test_sha256_vectors	4.322m	123.701ms	30	30	100.00
		hmac_test_sha384_vectors	10.386m	59.890ms	75	75	100.00
		hmac_test_sha512_vectors	9.456m	13.403ms	75	75	100.00
		hmac_test_hmac256_vectors	15.960s	1.335ms	50	50	100.00
		hmac_test_hmac384_vectors	18.580s	2.008ms	60	60	100.00
		hmac_test_hmac512_vectors	20.490s	390.899us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.990s	1.571ms	10	10	100.00
		hmac_long_msg	1.956m	6.436ms	10	10	100.00
		hmac_back_pressure	1.460m	1.853ms	25	25	100.00
		hmac_datapath_stress	10.613m	23.766ms	10	10	100.00
		hmac_burst_wr	50.440s	5.915ms	50	50	100.00
		hmac_error	1.613m	12.269ms	10	10	100.00
		hmac_wipe_secret	1.947m	36.945ms	10	10	100.00
		hmac_test_sha256_vectors	4.322m	123.701ms	30	30	100.00
		hmac_test_sha384_vectors	10.386m	59.890ms	75	75	100.00
		hmac_test_sha512_vectors	9.456m	13.403ms	75	75	100.00
		hmac_test_hmac256_vectors	15.960s	1.335ms	50	50	100.00
		hmac_test_hmac384_vectors	18.580s	2.008ms	60	60	100.00
		hmac_test_hmac512_vectors	20.490s	390.899us	75	75	100.00
		hmac_stress_all	26.317m	236.088ms	50	50	100.00
V2	stress_all	hmac_stress_all	26.317m	236.088ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.100s	52.791us	50	50	100.00
V2	intr_test	hmac_intr_test	2.210s	47.142us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.810s	355.648us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.810s	355.648us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.350s	148.418us	5	5	100.00
		hmac_csr_rw	2.440s	36.694us	20	20	100.00
		hmac_csr_aliasing	7.160s	306.051us	5	5	100.00
		hmac_same_csr_outstanding	4.200s	154.716us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.350s	148.418us	5	5	100.00
		hmac_csr_rw	2.440s	36.694us	20	20	100.00
		hmac_csr_aliasing	7.160s	306.051us	5	5	100.00
		hmac_same_csr_outstanding	4.200s	154.716us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.610s	160.651us	5	5	100.00
		hmac_tl_intg_err	5.920s	962.553us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.920s	962.553us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.990s	1.571ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	9.320s	151.833us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.846m	22.678ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.140s	34.399us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.95	99.84	97.14	100.00	100.00	99.83	99.52	47.30