I2C Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: `53e8d55`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.228m	1.976ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	40.420s	5.699ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.100s	20.622us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.180s	36.964us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.630s	1.082ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.760s	61.368us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.380s	40.392us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.180s	36.964us	20	20	100.00
		i2c_csr_aliasing	2.760s	61.368us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	20.690s	1.867ms	49	50	98.00
V2	host_stress_all	i2c_host_stress_all	46.829m	67.810ms	16	50	32.00
V2	host_maxperf	i2c_host_perf	19.627m	74.364ms	50	50	100.00
V2	host_override	i2c_host_override	2.260s	46.615us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.635m	21.929ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.246m	2.685ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.890s	685.401us	50	50	100.00
		i2c_host_fifo_fmt_empty	25.550s	503.641us	50	50	100.00
		i2c_host_fifo_reset_rx	13.410s	458.949us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.897m	3.335ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	44.790s	1.973ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	7.690s	726.714us	13	50	26.00
V2	target_glitch	i2c_target_glitch	11.310s	6.684ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	18.689m	58.457ms	49	50	98.00
V2	target_maxperf	i2c_target_perf	10.330s	1.109ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.284m	4.047ms	50	50	100.00
		i2c_target_intr_smoke	12.220s	6.898ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.330s	281.787us	50	50	100.00
		i2c_target_fifo_reset_tx	3.470s	345.615us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	23.481m	66.663ms	50	50	100.00
		i2c_target_stress_rd	1.284m	4.047ms	50	50	100.00
		i2c_target_intr_stress_wr	6.331m	25.522ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	10.810s	6.434ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	3.221m	5.598ms	47	50	94.00
V2	bad_address	i2c_target_bad_addr	9.540s	5.096ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	46.240s	10.154ms	21	50	42.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.720s	521.428us	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.250s	1.360ms	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	19.627m	74.364ms	50	50	100.00
		i2c_host_perf_precise	4.897m	23.507ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	44.790s	1.973ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	23.700s	1.943ms	46	50	92.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.460s	2.454ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.110s	6.101ms	50	50	100.00
		i2c_target_nack_txstretch	3.280s	265.565us	36	50	72.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	22.600s	677.874us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.410s	1.164ms	50	50	100.00
V2	alert_test	i2c_alert_test	2.230s	17.520us	50	50	100.00
V2	intr_test	i2c_intr_test	2.270s	18.829us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.240s	117.358us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.240s	117.358us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.100s	20.622us	5	5	100.00
		i2c_csr_rw	2.180s	36.964us	20	20	100.00
		i2c_csr_aliasing	2.760s	61.368us	5	5	100.00
		i2c_same_csr_outstanding	3.050s	1.878ms	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.100s	20.622us	5	5	100.00
		i2c_csr_rw	2.180s	36.964us	20	20	100.00
		i2c_csr_aliasing	2.760s	61.368us	5	5	100.00
		i2c_same_csr_outstanding	3.050s	1.878ms	20	20	100.00
V2		TOTAL			1668	1792	93.08
V2S	tl_intg_err	i2c_tl_intg_err	3.430s	126.816us	20	20	100.00
		i2c_sec_cm	2.560s	265.293us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.430s	126.816us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	49.060s	7.609ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.540s	178.609us	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	44.710s	5.687ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1848	2042	90.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.15	97.56	89.82	74.17	72.62	94.32	98.52	90.06

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 43 failures:

Test i2c_host_stress_all has 24 failures.

1.i2c_host_stress_all.109076068737264438782823590070198489878793445701829654983944668250485264475946
Line 214, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 30209177636 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2627254

4.i2c_host_stress_all.40685674660574603609127472523012106509015089322954221232781034554149273577364
Line 209, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 137154886051 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1792830

... and 22 more failures.

Test i2c_host_mode_toggle has 19 failures.

2.i2c_host_mode_toggle.5669758073499343678753994467915914560766366035319570016404124391600002451161
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 453616160 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @105137

5.i2c_host_mode_toggle.5971153520801673657677376761112403444450055322203348837463968384126196363114
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 726714205 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @170829

... and 17 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
- Test i2c_target_unexp_stop has 31 failures.
  - 0.i2c_target_unexp_stop.30740067485358969653258681694311309329925604658478757925765640768149838155715
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 677966012 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 90 [0x5a])
  UVM_INFO @ 677966012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.82856375949141205701503284713726156107388827779894915134899498490210465101377
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 217544874 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 204 [0xcc])
  UVM_INFO @ 217544874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 29 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_target_stress_all_with_rand_reset.36776986884754954171279333847199547625974351345181439328329823521548724322392
    Line 111, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 982546374 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 136 [0x88])
  UVM_INFO @ 982546374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 29 failures:
- Test i2c_target_hrst has 29 failures.
  - 1.i2c_target_hrst.31598573887947534075604582657119350220084015070398505316993195133029459823193
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10090211437 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10090211437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_hrst.10839339112615446011137951951688484980984338600916419219914355595537508400575
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10153526467 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10153526467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 27 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.63187047034173344043460756190235422852659106232100140237423947114585427430416
Line 143, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 572739521 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 572739521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.109531390524069263297283961507454929055096259590389449718804842181498693753309
Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1892782844 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1892782844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 6 failures.

4.i2c_target_stress_all_with_rand_reset.67107403596863343809741060295719679543714508046315266056649489578770208558051
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1047900105 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1047900105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.i2c_target_stress_all_with_rand_reset.22354969577920866113247393398321384746113499447270233084001080969197013576659
Line 156, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5686580612 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5686580612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 14 failures:
- Test i2c_target_nack_txstretch has 14 failures.
  - 6.i2c_target_nack_txstretch.115002783825495519941101690573263791421982714425542247535768386364698537513969
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 578242503 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 578242503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_nack_txstretch.43408369266630838714831036705323339791238568385713640396427583262070254979342
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 539918014 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 539918014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 13 failures:

Test i2c_host_mode_toggle has 12 failures.

3.i2c_host_mode_toggle.3893751029486538969968448272579806974989712973465898191816244544839412497600
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 135061386 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

6.i2c_host_mode_toggle.1715069662764142756253475561390414507515845611401590000188698450991651544369
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 157653158 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 10 more failures.

Test i2c_host_error_intr has 1 failures.

30.i2c_host_error_intr.91031046894174160113157155856754838723358398265485374409163271054482286143045
Line 137, in log /nightly/runs/scratch/master/i2c-sim-vcs/30.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 388844561 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 11 failures:
- Test i2c_target_unexp_stop has 11 failures.
  - 2.i2c_target_unexp_stop.88547993696662101093171380484328324369402669758835703787829473161448446764285
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 204148811 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 204148811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_unexp_stop.56644493465029466262073223972687149271295770050715392043818126865857281017318
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 573265841 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 573265841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 8 failures:

Test i2c_target_unexp_stop has 8 failures.

1.i2c_target_unexp_stop.94071864477660644530140321398081482573655638647395712235107142755214732440094
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 284242262 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 284242262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.i2c_target_unexp_stop.19490391922567102829540089044838507354983193198140020133061529158388482834550
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 121130125 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 121130125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 6 failures:
- Test i2c_host_mode_toggle has 6 failures.
  - 4.i2c_host_mode_toggle.80541358703637154080498248795323119337317038027007254247488252857459251367814
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 103892946 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x2c2d7d14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 103892946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.i2c_host_mode_toggle.37117610974072118029320581054425926375981848345616726198984202301553930626165
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  74942011 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x6334c794, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  74942011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 5 failures:

Test i2c_host_stress_all has 5 failures.

3.i2c_host_stress_all.98843544300779579735481856749476033095530054324645534784281465532017056572721
Line 161, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 86271707652 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4782220

33.i2c_host_stress_all.41530821202368251985645388866067742881479297445076329449287373363824513788834
Line 162, in log /nightly/runs/scratch/master/i2c-sim-vcs/33.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 37606637027 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @9539162

... and 3 more failures.

Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test i2c_target_tx_stretch_ctrl has 4 failures.
  - 18.i2c_target_tx_stretch_ctrl.80539172971697021704106745584498359776218679742798937705161995915167173986166
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 34.i2c_target_tx_stretch_ctrl.106231167038319328796029322381870926387286683380306107475978006269520796149204
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/34.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 2 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 3 failures:
- Test i2c_target_stretch has 3 failures.
  - 5.i2c_target_stretch.113588504449178259089371711362668792644635529853886828077697797751155184961197
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10026526857 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10026526857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 27.i2c_target_stretch.23976640473928671129885183543415807684999270412849199318201930436078542169710
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/27.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10006955214 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10006955214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Job timed out after * minutes has 2 failures:
- Test i2c_host_stress_all has 2 failures.
  - 0.i2c_host_stress_all.88034151665676825023420746066438654075333848803017328941044219783120723811221
    Log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 12.i2c_host_stress_all.108808440885726857631737010122020542474292336328751729800281578299154171297215
    Log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all has 1 failures.
  - 1.i2c_target_stress_all.32587015651266535651444317599441747204546619332278097587435307913171122447856
    Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 53205911243 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 53205911243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_intr_stress_wr has 1 failures.
  - 15.i2c_target_intr_stress_wr.69187146595099906610217190886301782768401803661233117696219770068523689413744
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 19242317281 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 19242317281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test i2c_host_stress_all has 2 failures.
  - 11.i2c_host_stress_all.86599790888883912116601298011498353248241232105286174781541910194402439895166
    Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.i2c_host_stress_all.53229110127195593519841082518603104305188915315470074400022423534761243738348
    Line 102, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.100057651648894571609476470146030966269491955169633843456436474965179472122871
    Line 102, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 212044286 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
  UVM_INFO @ 212044286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_target_stress_all_with_rand_reset.103626409947504366358536288505515316953613043133817995013183957472520620976542
    Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2415009239 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2415009239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 3.i2c_target_stress_all_with_rand_reset.26324950030255790781200143179114071532550117616182232200693951407475083385777
    Line 121, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4042304059 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_timeout_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
  UVM_INFO @ 4042304059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_host_stretch_timeout_vseq.sv:58) [i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + *) (* [*] vs * [*]) has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 25.i2c_host_stress_all.52674472388769035800792387354301640208764966389127846328645369888227094452218
    Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/25.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @  54117149 ps: (i2c_host_stretch_timeout_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.i2c_host_stretch_timeout_vseq] Check failed cnt_wr_stretch == (num_wr_bytes + 1) (0 [0x0] vs 2 [0x2])
  UVM_INFO @  54117149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```