KEYMGR Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: `53e8d55`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	24.150s	1.240ms	50	50	100.00
V1	random	keymgr_random	57.340s	8.637ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	3.090s	37.382us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.510s	54.038us	19	20	95.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.960s	1.736ms	2	5	40.00
V1	csr_aliasing	keymgr_csr_aliasing	12.390s	375.858us	2	5	40.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.160s	36.192us	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.510s	54.038us	19	20	95.00
		keymgr_csr_aliasing	12.390s	375.858us	2	5	40.00
V1		TOTAL			144	155	92.90
V2	cfgen_during_op	keymgr_cfg_regwen	1.635m	2.570ms	49	50	98.00
V2	sideload	keymgr_sideload	33.820s	5.129ms	50	50	100.00
		keymgr_sideload_kmac	42.830s	7.166ms	50	50	100.00
		keymgr_sideload_aes	40.770s	5.464ms	50	50	100.00
		keymgr_sideload_otbn	40.180s	5.176ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	31.600s	4.210ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	16.610s	457.855us	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	17.440s	813.327us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	40.130s	2.252ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	26.800s	2.020ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	20.130s	2.743ms	50	50	100.00
V2	stress_all	keymgr_stress_all	4.159m	64.322ms	48	50	96.00
V2	intr_test	keymgr_intr_test	2.380s	37.570us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.580s	27.873us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.020s	152.558us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.020s	152.558us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	3.090s	37.382us	5	5	100.00
		keymgr_csr_rw	2.510s	54.038us	19	20	95.00
		keymgr_csr_aliasing	12.390s	375.858us	2	5	40.00
		keymgr_same_csr_outstanding	3.950s	556.640us	14	20	70.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	3.090s	37.382us	5	5	100.00
		keymgr_csr_rw	2.510s	54.038us	19	20	95.00
		keymgr_csr_aliasing	12.390s	375.858us	2	5	40.00
		keymgr_same_csr_outstanding	3.950s	556.640us	14	20	70.00
V2		TOTAL			727	740	98.24
V2S	sec_cm_additional_check	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
		keymgr_tl_intg_err	7.450s	826.966us	14	20	70.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.110s	331.960us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.110s	331.960us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.110s	331.960us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.110s	331.960us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.740s	805.216us	11	20	55.00
V2S	prim_count_check	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.450s	826.966us	14	20	70.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.110s	331.960us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.635m	2.570ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	57.340s	8.637ms	50	50	100.00
		keymgr_csr_rw	2.510s	54.038us	19	20	95.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	57.340s	8.637ms	50	50	100.00
		keymgr_csr_rw	2.510s	54.038us	19	20	95.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	57.340s	8.637ms	50	50	100.00
		keymgr_csr_rw	2.510s	54.038us	19	20	95.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	16.610s	457.855us	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	26.800s	2.020ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	26.800s	2.020ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	57.340s	8.637ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	13.050s	706.565us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	10.240s	1.723ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	16.610s	457.855us	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	10.240s	1.723ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	10.240s	1.723ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	10.240s	1.723ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.200s	1.065ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	10.240s	1.723ms	50	50	100.00
V2S		TOTAL			150	165	90.91
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	19.990s	953.280us	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1044	1110	94.05

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.74	99.13	98.07	98.12	100.00	99.01	98.63	91.21

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 32 failures:

Test keymgr_tl_intg_err has 6 failures.

0.keymgr_tl_intg_err.38731057157911633012676611706527371845227673407962746496791053781634401551328
Line 104, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @ 144734188 ps: (keymgr_csr_assert_fpv.sv:419) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @ 144734188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_tl_intg_err.108599081607557925444053542211827711703224934624779330667626815062080853211311
Line 82, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @  89786377 ps: (keymgr_csr_assert_fpv.sv:394) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @  89786377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_bit_bash has 3 failures.

0.keymgr_csr_bit_bash.72795048162467736743737104578392792250853045238987543623095833751389999537855
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @ 4285576376 ps: (keymgr_csr_assert_fpv.sv:409) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @ 4285576376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_csr_bit_bash.24784035980275286976219142132495942513609735161609376024401064978174782012194
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @ 110655301 ps: (keymgr_csr_assert_fpv.sv:429) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @ 110655301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_csr_aliasing has 3 failures.

0.keymgr_csr_aliasing.30378336675997244935338969295524924944282836423308310842521313286202956673626
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @ 112287188 ps: (keymgr_csr_assert_fpv.sv:459) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @ 112287188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_csr_aliasing.75718185849005631713456206369136818043962882699525214845534933829173058495670
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @ 343498099 ps: (keymgr_csr_assert_fpv.sv:394) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @ 343498099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_csr_mem_rw_with_rand_reset has 4 failures.

0.keymgr_csr_mem_rw_with_rand_reset.88217506501088201708848627646315269771629190675126084144545896064549664889659
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  15853557 ps: (keymgr_csr_assert_fpv.sv:449) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  15853557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.keymgr_csr_mem_rw_with_rand_reset.73491388621778618494118444862664215491766211827482504133318330311547851755513
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  28521098 ps: (keymgr_csr_assert_fpv.sv:449) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  28521098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test keymgr_same_csr_outstanding has 6 failures.

1.keymgr_same_csr_outstanding.47686457525684853209977231445323562479510631009560941759166874110495586754562
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @  62052865 ps: (keymgr_csr_assert_fpv.sv:409) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @  62052865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_same_csr_outstanding.110199739469645160473425531581835287428496181504779254132502203698867852363979
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  35836965 ps: (keymgr_csr_assert_fpv.sv:404) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  35836965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test keymgr_stress_all_with_rand_reset has 26 failures.
  - 0.keymgr_stress_all_with_rand_reset.27385155773130000520364893407344307661052426425805123639162391056923473197608
    Line 350, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2643634948 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2643634948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.72741165591468122193842233094119137515291527519946538151245739381873708058124
    Line 2114, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9843510957 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9843510957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 24 more failures.

UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_stress_all has 2 failures.

9.keymgr_stress_all.12191895393324894138147955055118362635427541429474936785231184925136969222102
Line 89, in log /nightly/runs/scratch/master/keymgr-sim-vcs/9.keymgr_stress_all/latest/run.log

  UVM_ERROR @   7106257 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   7106257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.keymgr_stress_all.5179123473022405580102040928602718637220109440403085366007479023005315229101
Line 400, in log /nightly/runs/scratch/master/keymgr-sim-vcs/12.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 263650955 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 263650955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_hwsw_invalid_input has 1 failures.

44.keymgr_hwsw_invalid_input.114606530011189258666465793272083441116629176522192932512148764020834011821547
Line 202, in log /nightly/runs/scratch/master/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest/run.log

  UVM_ERROR @  25381504 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  25381504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 1.keymgr_lc_disable.68395431526931759611960672552859668939424730713899250233105745728754609802951
    Line 346, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @ 177240797 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (5 [0x5] vs 6 [0x6])
  UVM_INFO @ 177240797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 26.keymgr_kmac_rsp_err.39968900190153222164929746785659463162085567098508184086938470458969629764918
    Line 168, in log /nightly/runs/scratch/master/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  13293819 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  13293819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

34.keymgr_lc_disable.49416875100878637325009255693418377161737475426742593732702560494693629064592
Line 325, in log /nightly/runs/scratch/master/keymgr-sim-vcs/34.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 253945088 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10033603675398164168006591827882791182245946066826720667191380841965322292492424650992434090176089050349460801256688280362631441583961280707707556958160356 [0xbf933bb05d754ba5ebcfb3351938157e7c9991cf673fb762e389c355b59ee42a9036d1bb3fb04b1674a8e8d69b052aeb82d489ef76f7ce5dac4f44aadc59c5e4] vs 10033603675398164168006591827882791182245946066826720667191380841965322292492424650992434090176089050349460801256688280362631441583961280707707556958160356 [0xbf933bb05d754ba5ebcfb3351938157e7c9991cf673fb762e389c355b59ee42a9036d1bb3fb04b1674a8e8d69b052aeb82d489ef76f7ce5dac4f44aadc59c5e4]) KMAC key at state StDisabled for Attestation Kmac
  UVM_INFO @ 253945088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_stress_all_with_rand_reset has 1 failures.

35.keymgr_stress_all_with_rand_reset.16138171350975958430329442258631779377303011529155552443072273622092480469904
Line 668, in log /nightly/runs/scratch/master/keymgr-sim-vcs/35.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1031973214 ps: (keymgr_scoreboard.sv:1064) [uvm_test_top.env.scoreboard] Check failed act == exp (47492792791250359114962500302868396360506675188134999171125464987859735554056983871578561550880413927702282497835591023388332422336814273593266401720790259516397020936748691451285937607078067930896382584241675374814935760644237275189328406650999569351136652351131401097664566404026052599955266982657603235352895993060724495885511060321996013482745 [0xc6c0a5e99bfe496b00000000afe6c0c900000000000000000000000000000000d2dadd6956079e5442aea6126f98397c267138c1acbbc0536a272af8a3a3f4b0b8a157c7f8a37cf7da8b7069c8ac3fea39a39c4c3d2a54abc035184ee6fc5becb721ea7e64dd4b300d8a3c863c36bf4a3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9] vs 6661519625021623631975382298845749024629356508371217125644317627415955947121897402366547308720735634742671861178128134578382931643708470645931816139537755418084033578044884546433161098108708958739664147462945444998774959928550210480953243550137583143787536000789937146343873979283591045375918506609597067002699712119081522208925051695865 [0x77bbf305caf1e11900000000b981dd7e9c9e1051000000001afe0993d2dadd6956079e5442aea6126f98397c267138c1acbbc0536a272af8a3a3f4b0b8a157c7f8a37cf7da8b7069c8ac3fea39a39c4c3d2a54abc035184ee6fc5becb721ea7e64dd4b300d8a3c863c36bf4a3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9]) cdi_type: Attestation

   HardwareRevisionSecret act: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9, exp: 0x3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9
   RomDigest act: 0x39a39c4c3d2a54abc035184ee6fc5becb721ea7e64dd4b300d8a3c863c36bf4a, exp: 0x39a39c4c3d2a54abc035184ee6fc5becb721ea7e64dd4b300d8a3c863c36bf4a
   HealthMeasurement act: 0xb8a157c7f8a37cf7da8b7069c8ac3fea, exp: 0xb8a157c7f8a37cf7da8b7069c8ac3fea

UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 41.keymgr_cfg_regwen.104234585734290641593225318089525550177116462412961513978423050631543681739576
    Line 123, in log /nightly/runs/scratch/master/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @   9819610 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   9819610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```