KEYMGR_DPE Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	2.500m	79.147ms	48	50	96.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	2.490s	15.334us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	2.670s	143.320us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	20.510s	5.691ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	11.010s	1.155ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	3.330s	39.697us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	2.670s	143.320us	20	20	100.00
		keymgr_dpe_csr_aliasing	11.010s	1.155ms	5	5	100.00
V1		TOTAL			103	105	98.10
V2	intr_test	keymgr_dpe_intr_test	2.470s	14.861us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	2.570s	24.750us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	5.950s	1.571ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	5.950s	1.571ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	2.490s	15.334us	5	5	100.00
		keymgr_dpe_csr_rw	2.670s	143.320us	20	20	100.00
		keymgr_dpe_csr_aliasing	11.010s	1.155ms	5	5	100.00
		keymgr_dpe_same_csr_outstanding	4.360s	953.496us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	2.490s	15.334us	5	5	100.00
		keymgr_dpe_csr_rw	2.670s	143.320us	20	20	100.00
		keymgr_dpe_csr_aliasing	11.010s	1.155ms	5	5	100.00
		keymgr_dpe_same_csr_outstanding	4.360s	953.496us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	16.450s	1.263ms	5	5	100.00
		keymgr_dpe_tl_intg_err	6.470s	339.130us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	5.610s	305.521us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	5.610s	305.521us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	5.610s	305.521us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	5.610s	305.521us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	10.320s	1.641ms	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	16.450s	1.263ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	16.450s	1.263ms	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			308	310	99.35

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.07	97.63	90.66	63.14	76.92	94.89	98.57	17.68

Failure Buckets

• UVM_ERROR (keymgr_dpe_scoreboard.sv:565) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 1 failures:

  • Test keymgr_dpe_smoke has 1 failures.

    • 28.keymgr_dpe_smoke.67658739403530437923678730023805820753820544726915294319119243862217373619026
      Line 2631, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/28.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 1768620943 ps: (keymgr_dpe_scoreboard.sv:565) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h1fc9bc79afc7cbf05349ae9000a71d42db3b193b5ac69e084db1bfd2c5fd2c5d4b6700a17061cd00ac49a830123b14ba5f46d574e9081e43bc31397c0db20986 vs. act 'h0
        UVM_INFO @ 1768620943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:

  • Test keymgr_dpe_smoke has 1 failures.

    • 32.keymgr_dpe_smoke.105308754794717645200783738525627891054803247068693982981213313629047617907580
      Line 908, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/32.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @  73202655 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @  73202655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---