KMAC/MASKED Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.633m	23.980ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.520s	94.876us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.770s	28.162us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.190s	1.458ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.520s	540.429us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.030s	79.986us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.770s	28.162us	20	20	100.00
		kmac_csr_aliasing	9.520s	540.429us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.330s	11.993us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.970s	35.914us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.592m	381.507ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.974m	216.288ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.826m	94.257ms	5	5	100.00
		kmac_test_vectors_sha3_256	35.238m	487.763ms	5	5	100.00
		kmac_test_vectors_sha3_384	23.640m	114.875ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.302m	369.429ms	5	5	100.00
		kmac_test_vectors_shake_128	44.577m	451.617ms	5	5	100.00
		kmac_test_vectors_shake_256	6.720m	101.747ms	5	5	100.00
		kmac_test_vectors_kmac	4.750s	104.132us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.900s	113.360us	5	5	100.00
V2	sideload	kmac_sideload	8.422m	71.729ms	50	50	100.00
V2	app	kmac_app	6.549m	14.921ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.116m	84.528ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.611m	295.460ms	50	50	100.00
V2	error	kmac_error	7.776m	71.850ms	50	50	100.00
V2	key_error	kmac_key_error	19.090s	6.101ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.240s	500.636us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.250s	14.556ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.000s	1.319ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.616m	8.229ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.230s	1.234ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.644m	42.745ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.600s	29.758us	50	50	100.00
V2	alert_test	kmac_alert_test	2.410s	25.853us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.910s	575.433us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.910s	575.433us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.520s	94.876us	5	5	100.00
		kmac_csr_rw	2.770s	28.162us	20	20	100.00
		kmac_csr_aliasing	9.520s	540.429us	5	5	100.00
		kmac_same_csr_outstanding	3.960s	110.859us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.520s	94.876us	5	5	100.00
		kmac_csr_rw	2.770s	28.162us	20	20	100.00
		kmac_csr_aliasing	9.520s	540.429us	5	5	100.00
		kmac_same_csr_outstanding	3.960s	110.859us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.500s	943.944us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.500s	943.944us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.500s	943.944us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.500s	943.944us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.310s	215.186us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	1.477m	62.699ms	5	5	100.00
		kmac_tl_intg_err	5.280s	743.817us	13	20	65.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.280s	743.817us	13	20	65.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.230s	1.234ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.633m	23.980ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.422m	71.729ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.500s	943.944us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.477m	62.699ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.477m	62.699ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.477m	62.699ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.633m	23.980ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.230s	1.234ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.477m	62.699ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.119m	43.234ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.633m	23.980ms	50	50	100.00
V2S		TOTAL			61	75	81.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.863m	9.663ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			921	940	97.98

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.44	99.14	94.47	99.89	80.28	97.09	99.37	97.86

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 14 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.86621062206184400063042321380368690260834757297471789769999868444985144440117
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
        UVM_ERROR @ 140163395 ps: (kmac_csr_assert_fpv.sv:500) [ASSERT FAILED] prefix_1_rd_A
        UVM_INFO @ 140163395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.kmac_shadow_reg_errors_with_csr_rw.112657372593480630808124776399000592775589725899806529746428068260083768220377
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
        UVM_ERROR @  10862122 ps: (kmac_csr_assert_fpv.sv:490) [ASSERT FAILED] entropy_period_rd_A
        UVM_INFO @  10862122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

  • Test kmac_tl_intg_err has 7 failures.

    • 3.kmac_tl_intg_err.24866098295698189634170125417602943147046576501742683300920498711410794719422
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
        UVM_ERROR @  15594232 ps: (kmac_csr_assert_fpv.sv:525) [ASSERT FAILED] prefix_6_rd_A
        UVM_INFO @  15594232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.kmac_tl_intg_err.75563266837878110770666984984675689605114711845751638169055648515755815686820
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  11512133 ps: (kmac_csr_assert_fpv.sv:510) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  11512133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
  • Test kmac_stress_all_with_rand_reset has 5 failures.

    • 0.kmac_stress_all_with_rand_reset.38834588389433033381904234997291562626177090651860009536344467788358301298737
      Line 107, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1621964475 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1621964475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.kmac_stress_all_with_rand_reset.69018568698990839071124060433079887721481839499774426562631075355756696016415
      Line 94, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1001907340 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1001907340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.