KMAC/UNMASKED Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: `53e8d55`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.210m	34.373ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.600s	142.429us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.570s	49.563us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.150s	1.036ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.200s	395.671us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.620s	297.101us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.570s	49.563us	20	20	100.00
		kmac_csr_aliasing	9.200s	395.671us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.350s	22.078us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.920s	37.934us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	48.107m	241.107ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.270m	117.339ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.048m	190.788ms	5	5	100.00
		kmac_test_vectors_sha3_256	27.490m	584.374ms	5	5	100.00
		kmac_test_vectors_sha3_384	22.046m	267.897ms	5	5	100.00
		kmac_test_vectors_sha3_512	14.938m	49.220ms	5	5	100.00
		kmac_test_vectors_shake_128	3.890m	14.511ms	5	5	100.00
		kmac_test_vectors_shake_256	29.137m	339.123ms	5	5	100.00
		kmac_test_vectors_kmac	4.390s	919.681us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.290s	335.240us	5	5	100.00
V2	sideload	kmac_sideload	7.376m	42.143ms	50	50	100.00
V2	app	kmac_app	6.487m	18.977ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.470m	18.759ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.165m	82.888ms	50	50	100.00
V2	error	kmac_error	6.512m	38.045ms	49	50	98.00
V2	key_error	kmac_key_error	15.400s	9.767ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.668m	10.006ms	41	50	82.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.930s	962.858us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.390s	6.909ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	51.740s	26.991ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	23.520s	1.782ms	50	50	100.00
V2	stress_all	kmac_stress_all	27.408m	173.790ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.390s	19.321us	50	50	100.00
V2	alert_test	kmac_alert_test	2.330s	19.310us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.020s	651.630us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.020s	651.630us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.600s	142.429us	5	5	100.00
		kmac_csr_rw	2.570s	49.563us	20	20	100.00
		kmac_csr_aliasing	9.200s	395.671us	5	5	100.00
		kmac_same_csr_outstanding	3.840s	110.916us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.600s	142.429us	5	5	100.00
		kmac_csr_rw	2.570s	49.563us	20	20	100.00
		kmac_csr_aliasing	9.200s	395.671us	5	5	100.00
		kmac_same_csr_outstanding	3.840s	110.916us	20	20	100.00
V2		TOTAL			730	740	98.65
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.650s	330.747us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.650s	330.747us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.650s	330.747us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.650s	330.747us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.060s	300.128us	12	20	60.00
V2S	tl_intg_err	kmac_sec_cm	1.148m	22.577ms	5	5	100.00
		kmac_tl_intg_err	6.360s	235.044us	16	20	80.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.360s	235.044us	16	20	80.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	23.520s	1.782ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.210m	34.373ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.376m	42.143ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.650s	330.747us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.148m	22.577ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.148m	22.577ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.148m	22.577ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.210m	34.373ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	23.520s	1.782ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.148m	22.577ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.414m	18.874ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.210m	34.373ms	50	50	100.00
V2S		TOTAL			63	75	84.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.293m	15.472ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			913	940	97.13

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.95	97.23	94.42	100.00	74.38	95.98	99.35	96.27

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 8 failures.

2.kmac_shadow_reg_errors_with_csr_rw.13260693624918260549775579952557671508968659873747078184498417987700526933128
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @   6783207 ps: (kmac_csr_assert_fpv.sv:515) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @   6783207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.77940354156471726070269834382635672366222726064790210924918980837327089385113
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @ 185354538 ps: (kmac_csr_assert_fpv.sv:520) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @ 185354538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test kmac_tl_intg_err has 4 failures.

6.kmac_tl_intg_err.71933398588118195640375984616093255118850258056715919883947611447708409055408
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  32954763 ps: (kmac_csr_assert_fpv.sv:500) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  32954763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_tl_intg_err.96722191594253604574531011522398081557819689412707985403745061781769012349759
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  85381869 ps: (kmac_csr_assert_fpv.sv:540) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  85381869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.64750801914259405344888321819139261181633619009194212082555824641579784893740
    Line 137, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24586885608 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 24586885608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.4072555798406260429814900958924385220031258137296935337882527972930572911875
    Line 212, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16079389325 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 16079389325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 19.kmac_sideload_invalid.77792919518013700615306043142143728581553168589484822631564176997657146805938
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10006014168 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1052a000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10006014168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 36.kmac_sideload_invalid.26628083914517269533467552434737426802834912149878495702462778572374775127693
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/36.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10038869821 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9ca4000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10038869821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 25.kmac_sideload_invalid.34214379722472611412771259228727299512378017413022573419498298213721289285913
    Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10512657831 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3dabf000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
  UVM_INFO @ 10512657831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 27.kmac_sideload_invalid.68984919791765946166783022172009385171983557458925664615575448109108303804969
    Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/27.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10269708038 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xadb8b000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
  UVM_INFO @ 10269708038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 3.kmac_sideload_invalid.20014323510826040377394475303785851917543360907535770585879438346135151461435
    Line 88, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10470792338 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x27fb8000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
  UVM_INFO @ 10470792338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 6.kmac_sideload_invalid.10327295897010307166832200834953641592505188981374523553334602613116057970689
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10173581500 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcab87000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10173581500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 6.kmac_error.62274831076496772005485998467762554260058191806763819508742051108247771003120
    Line 184, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 8.kmac_sideload_invalid.28229013262496818479919180040675211668919855673147809414160165009548095427532
    Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10389120270 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x69cde000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
  UVM_INFO @ 10389120270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 42.kmac_sideload_invalid.105099954068049827263309976683170154777502245711654492501369090683901847484560
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10064390364 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x31f42000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10064390364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 43.kmac_sideload_invalid.17937197197409381648125017024118614082779187337751740980948246493778425710810
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/43.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10021508241 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfec74000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10021508241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```