MBX Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 mbx_smoke mbx_smoke 46.000s 2.960ms 2 2 100.00
V1 csr_hw_reset mbx_csr_hw_reset 5.000s 25.497us 5 5 100.00
V1 csr_rw mbx_csr_rw 5.000s 31.903us 20 20 100.00
V1 csr_bit_bash mbx_csr_bit_bash 5.000s 114.752us 5 5 100.00
V1 csr_aliasing mbx_csr_aliasing 10.000s 24.289us 5 5 100.00
V1 csr_mem_rw_with_rand_reset mbx_csr_mem_rw_with_rand_reset 5.000s 4.246us 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr mbx_csr_rw 5.000s 31.903us 20 20 100.00
mbx_csr_aliasing 10.000s 24.289us 5 5 100.00
V1 TOTAL 37 57 64.91
V2 mbx_stress mbx_stress 3.000m 62.822ms 2 2 100.00
mbx_stress_zero_delays 1.850m 8.740ms 2 2 100.00
V2 mbx_imbx_oob mbx_imbx_oob 23.000s 342.365us 2 2 100.00
V2 alert_test mbx_alert_test 5.000s 25.081us 50 50 100.00
V2 tl_d_oob_addr_access mbx_tl_errors 5.000s 3.934us 0 20 0.00
V2 tl_d_illegal_access mbx_tl_errors 5.000s 3.934us 0 20 0.00
V2 tl_d_outstanding_access mbx_csr_hw_reset 5.000s 25.497us 5 5 100.00
mbx_csr_rw 5.000s 31.903us 20 20 100.00
mbx_csr_aliasing 10.000s 24.289us 5 5 100.00
mbx_same_csr_outstanding 5.000s 51.404us 20 20 100.00
V2 tl_d_partial_access mbx_csr_hw_reset 5.000s 25.497us 5 5 100.00
mbx_csr_rw 5.000s 31.903us 20 20 100.00
mbx_csr_aliasing 10.000s 24.289us 5 5 100.00
mbx_same_csr_outstanding 5.000s 51.404us 20 20 100.00
V2 TOTAL 76 96 79.17
V2S tl_intg_err mbx_sec_cm 5.000s 19.256us 5 5 100.00
mbx_tl_intg_err 5.000s 70.589us 0 20 0.00
V2S TOTAL 5 25 20.00
TOTAL 118 178 66.29

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
90.49 96.68 91.89 96.49 80.03 85.25 -- 98.54 65.23

Failure Buckets