OTBN Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: `53e8d55`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	22.000s	94.576us	1	1	100.00
V1	single_binary	otbn_single	2.950m	734.756us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	20.926us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	12.915us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	12.000s	41.759us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	27.160us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	27.904us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	12.915us	20	20	100.00
		otbn_csr_aliasing	7.000s	27.160us	5	5	100.00
V1	mem_walk	otbn_mem_walk	33.000s	1.620ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	15.000s	454.968us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	42.000s	95.199us	10	10	100.00
V2	multi_error	otbn_multi_err	1.100m	268.782us	1	1	100.00
V2	back_to_back	otbn_multi	4.917m	1.076ms	10	10	100.00
V2	stress_all	otbn_stress_all	1.450m	360.462us	10	10	100.00
V2	lc_escalation	otbn_escalate	26.000s	76.980us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	11.000s	15.725us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	20.000s	80.987us	10	10	100.00
V2	alert_test	otbn_alert_test	8.000s	22.291us	50	50	100.00
V2	intr_test	otbn_intr_test	10.000s	28.636us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	129.142us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	129.142us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	20.926us	5	5	100.00
		otbn_csr_rw	7.000s	12.915us	20	20	100.00
		otbn_csr_aliasing	7.000s	27.160us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	20.110us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	20.926us	5	5	100.00
		otbn_csr_rw	7.000s	12.915us	20	20	100.00
		otbn_csr_aliasing	7.000s	27.160us	5	5	100.00
		otbn_same_csr_outstanding	7.000s	20.110us	20	20	100.00
V2		TOTAL			245	246	99.59
V2S	mem_integrity	otbn_imem_err	17.000s	51.527us	10	10	100.00
		otbn_dmem_err	24.000s	85.176us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	19.000s	66.594us	5	5	100.00
		otbn_controller_ispr_rdata_err	19.000s	67.052us	5	5	100.00
		otbn_mac_bignum_acc_err	2.567m	472.395us	5	5	100.00
		otbn_urnd_err	12.000s	30.818us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	12.000s	16.203us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	22.853us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	10.000s	29.835us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
		otbn_tl_intg_err	1.000m	292.977us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	42.000s	231.265us	18	20	90.00
V2S	prim_fsm_check	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	22.000s	94.576us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	24.000s	85.176us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	17.000s	51.527us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.000m	292.977us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	26.000s	76.980us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	17.000s	51.527us	10	10	100.00
		otbn_dmem_err	24.000s	85.176us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	15.725us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	16.203us	5	5	100.00
		otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.950m	734.756us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	17.000s	51.527us	10	10	100.00
		otbn_dmem_err	24.000s	85.176us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	15.725us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	16.203us	5	5	100.00
		otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	26.000s	76.980us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	17.000s	51.527us	10	10	100.00
		otbn_dmem_err	24.000s	85.176us	15	15	100.00
		otbn_zero_state_err_urnd	11.000s	15.725us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	16.203us	5	5	100.00
		otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.950m	734.756us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	30.939us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	15.000s	44.486us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.033m	227.787us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.033m	227.787us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	28.000s	326.276us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	19.000s	222.378us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	44.018us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	22.000s	44.018us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	11.071us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.950m	734.756us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.950m	734.756us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.950m	734.756us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	4.917m	1.076ms	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.950m	734.756us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.950m	734.756us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	15.000s	32.161us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.950m	734.756us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.900m	2.383ms	4	5	80.00
V2S		TOTAL			157	163	96.32
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	10.617m	10.068ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			571	585	97.61

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.12	99.64	96.04	99.73	93.32	93.62	100.00	98.18	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 0.otbn_stress_all_with_rand_reset.33367284770518504848572246567141533366776532790756135772822386334622835544971
    Line 201, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4812723062 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4812723062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.otbn_stress_all_with_rand_reset.13012868332312416125083897482464509560002402910089925866286260878433037812348
    Line 268, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 623169654 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 623169654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_sec_wipe_err has 3 failures.

0.otbn_sec_wipe_err.58005450122046827158023601943321306654220447302480030845977826329170749116801
Line 106, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 11070738 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  11070738 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  11070738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_sec_wipe_err.113525852320213378844573897875503808410965827520871310405215458038347408475780
Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 9094130 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @   9094130 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   9094130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 3 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

4.otbn_stress_all_with_rand_reset.58706186297701207582966333198950133447223435248606369044995228241393703680708
Line 182, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 862137670 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @ 862137670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_passthru_mem_tl_intg_err has 2 failures.

4.otbn_passthru_mem_tl_intg_err.57718674441935885388797607035088926853805299429422667734240943198410369511689
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @  10246658 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  10246658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.otbn_passthru_mem_tl_intg_err.47719861264350034411536931503074185057419560408639416397522868337442633978083
Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/13.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @  40548135 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  40548135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 2 failures:
- Test otbn_stress_all_with_rand_reset has 2 failures.
  - 6.otbn_stress_all_with_rand_reset.59734950351824381669351526229532784234774036898057868776245351778868241924509
    Line 166, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 379308856 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 379308856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.otbn_stress_all_with_rand_reset.77785809767466474010343816763912389316779742150692539021615526699572289558735
    Line 140, in log /nightly/runs/scratch/master/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   5098220 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @   5098220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.42779292429512808186953709756237319539608997452748885238556645295137349015348
    Line 164, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  37434311 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  37434311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

1.otbn_sec_cm.67980251650182630568788869624411931458895845091631362721428465835613295051593
Line 117, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 69010091 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 69010091 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  69010091 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  69010091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 1 failures:
- Test otbn_escalate has 1 failures.
  - 20.otbn_escalate.53651889812688020325290962896733413694492607801438827680640247347220868704638
    Line 102, in log /nightly/runs/scratch/master/otbn-sim-xcelium/20.otbn_escalate/latest/run.log
```
  UVM_ERROR @   5751470 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   5751470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```