ROM_CTRL/32KB Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.570s	135.158us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.110s	291.541us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	8.120s	176.669us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.890s	1.022ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.740s	168.788us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.840s	871.056us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	8.120s	176.669us	20	20	100.00
		rom_ctrl_csr_aliasing	7.740s	168.788us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.080s	499.664us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.430s	128.076us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.630s	137.090us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	28.400s	2.335ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	13.590s	300.686us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.220s	164.744us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.340s	168.573us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.340s	168.573us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.110s	291.541us	5	5	100.00
		rom_ctrl_csr_rw	8.120s	176.669us	20	20	100.00
		rom_ctrl_csr_aliasing	7.740s	168.788us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.530s	9.949ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.110s	291.541us	5	5	100.00
		rom_ctrl_csr_rw	8.120s	176.669us	20	20	100.00
		rom_ctrl_csr_aliasing	7.740s	168.788us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.530s	9.949ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.791m	1.865ms	19	20	95.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	32.640s	1.569ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.986m	597.092us	5	5	100.00
		rom_ctrl_tl_intg_err	1.008m	277.049us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.986m	597.092us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.986m	597.092us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.791m	1.865ms	19	20	95.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.791m	1.865ms	19	20	95.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.791m	1.865ms	19	20	95.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.791m	1.865ms	19	20	95.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.791m	1.865ms	19	20	95.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.986m	597.092us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.986m	597.092us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.570s	135.158us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.570s	135.158us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.570s	135.158us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.008m	277.049us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.791m	1.865ms	19	20	95.00
		rom_ctrl_kmac_err_chk	13.590s	300.686us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.791m	1.865ms	19	20	95.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.791m	1.865ms	19	20	95.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.791m	1.865ms	19	20	95.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	32.640s	1.569ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.986m	597.092us	5	5	100.00
V2S		TOTAL			64	65	98.46
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.293m	18.926ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			265	266	99.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	100.00	99.41	100.00	100.00	100.00	98.97	99.05

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 9.rom_ctrl_corrupt_sig_fatal_chk.27798051030766405641245083783149408611177507958889434995846165615913544088054
      Line 105, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/9.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 8030955531 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 8030955531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---