RV_TIMER Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.780s	17.491us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.790s	16.743us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.110s	15.980us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.320s	428.608us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.950s	38.995us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.710s	78.000us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.110s	15.980us	20	20	100.00
		rv_timer_csr_aliasing	1.950s	38.995us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	12.250s	59.647ms	20	20	100.00
V2	disabled	rv_timer_disabled	4.720s	2.723ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	10.804m	484.588ms	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	10.804m	484.588ms	10	10	100.00
V2	stress	rv_timer_stress_all	9.060s	5.539ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	2.090s	12.662us	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.070s	12.227us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.580s	562.062us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.580s	562.062us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.790s	16.743us	5	5	100.00
		rv_timer_csr_rw	2.110s	15.980us	20	20	100.00
		rv_timer_csr_aliasing	1.950s	38.995us	5	5	100.00
		rv_timer_same_csr_outstanding	2.090s	264.188us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.790s	16.743us	5	5	100.00
		rv_timer_csr_rw	2.110s	15.980us	20	20	100.00
		rv_timer_csr_aliasing	1.950s	38.995us	5	5	100.00
		rv_timer_same_csr_outstanding	2.090s	264.188us	20	20	100.00
V2		TOTAL			210	210	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.050s	244.311us	5	5	100.00
		rv_timer_tl_intg_err	2.960s	3.017ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.960s	3.017ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	54.480s	54.915ms	20	20	100.00
V3		TOTAL			20	20	100.00
	Unmapped tests	rv_timer_min	1.790s	14.205us	10	10	100.00
		rv_timer_max	1.810s	14.497us	10	10	100.00
		TOTAL			350	350	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
100.00	100.00	100.00	100.00	--	100.00	100.00	100.00