SPI_DEVICE/1R1W Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: `53e8d55`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.022m	65.318ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.860s	73.366us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.240s	42.077us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.280s	10.849ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.700s	2.891ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.240s	166.505us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.240s	42.077us	20	20	100.00
		spi_device_csr_aliasing	16.700s	2.891ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.220s	13.515us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.810s	193.380us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.400s	51.123us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.380s	4.166us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.820s	4.543us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	10.460s	579.097us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.460s	579.097us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	32.610s	16.456ms	50	50	100.00
		spi_device_tpm_sts_read	2.630s	129.716us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	51.680s	9.630ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	33.670s	46.021ms	50	50	100.00
		spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.328m	82.912ms	50	50	100.00
		spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.328m	82.912ms	50	50	100.00
		spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.990s	3.586ms	50	50	100.00
		spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.990s	3.586ms	50	50	100.00
		spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.990s	3.586ms	50	50	100.00
		spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.990s	3.586ms	50	50	100.00
		spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.990s	3.586ms	50	50	100.00
		spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	45.700s	10.675ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.126m	81.325ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.126m	81.325ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.126m	81.325ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.070m	21.103ms	50	50	100.00
		spi_device_read_buffer_direct	25.300s	4.485ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.126m	81.325ms	50	50	100.00
		spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.285m	269.585ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.280s	10.030ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.280s	10.030ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.022m	65.318ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.423m	48.956ms	50	50	100.00
V2	stress_all	spi_device_stress_all	2.603h	10.000s	49	50	98.00
V2	alert_test	spi_device_alert_test	2.370s	65.142us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.400s	61.698us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.020s	785.820us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.020s	785.820us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.860s	73.366us	5	5	100.00
		spi_device_csr_rw	4.240s	42.077us	20	20	100.00
		spi_device_csr_aliasing	16.700s	2.891ms	5	5	100.00
		spi_device_same_csr_outstanding	6.030s	782.045us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.860s	73.366us	5	5	100.00
		spi_device_csr_rw	4.240s	42.077us	20	20	100.00
		spi_device_csr_aliasing	16.700s	2.891ms	5	5	100.00
		spi_device_same_csr_outstanding	6.030s	782.045us	20	20	100.00
V2		TOTAL			939	961	97.71
V2S	tl_intg_err	spi_device_sec_cm	2.910s	86.173us	5	5	100.00
		spi_device_tl_intg_err	26.400s	13.030ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	26.400s	13.030ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	49.572m	1.500s	49	50	98.00
		TOTAL			1128	1151	98.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.55	99.11	96.55	83.54	89.36	98.39	95.66	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.72537300082661710135795988998846334417062665905396899527932591586646211665806
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1020795 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[31])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1020795 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1020795 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[927])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.4609373223125549502769082906849124526248690506552346108115491525548139592120
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   9732726 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[55])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   9732726 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   9732726 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[951])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test spi_device_stress_all has 1 failures.
  - 16.spi_device_stress_all.11853508882329708706382008898449507244010499758204569608449361953070911498291
    Line 126, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 36.spi_device_flash_mode_ignore_cmds.106673169186627440111262101026382319422033252235988167483425562195276859050392
    Line 78, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.106849642962684409847750311314876530017374262081859699653984598460155631506838
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   2043526 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x64254f [11001000010010101001111] vs 0x0 [0])
  UVM_ERROR @   2095526 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3b1262 [1110110001001001100010] vs 0x0 [0])
  UVM_ERROR @   2117526 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8941c [10001001010000011100] vs 0x0 [0])
  UVM_ERROR @   2148526 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x94579 [10010100010101111001] vs 0x0 [0])
  UVM_ERROR @   2239526 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd9d83c [110110011101100000111100] vs 0x0 [0])