SPI_HOST Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: `53e8d55`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.150m	12.175ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	51.497us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	52.151us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	234.580us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	80.507us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	49.294us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	52.151us	20	20	100.00
		spi_host_csr_aliasing	5.000s	80.507us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	35.695us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	55.192us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	36.000s	23.875us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	45.000s	1.695ms	50	50	100.00
		spi_host_error_cmd	6.000s	59.525us	50	50	100.00
		spi_host_event	13.367m	24.737ms	50	50	100.00
V2	clock_rate	spi_host_speed	35.000s	42.692us	50	50	100.00
V2	speed	spi_host_speed	35.000s	42.692us	50	50	100.00
V2	chip_select_timing	spi_host_speed	35.000s	42.692us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	1.850m	8.691ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	79.726us	50	50	100.00
V2	cpol_cpha	spi_host_speed	35.000s	42.692us	50	50	100.00
V2	full_cycle	spi_host_speed	35.000s	42.692us	50	50	100.00
V2	duplex	spi_host_smoke	2.150m	12.175ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	2.150m	12.175ms	50	50	100.00
V2	stress_all	spi_host_stress_all	2.217m	17.648ms	50	50	100.00
V2	spien	spi_host_spien	2.200m	7.625ms	50	50	100.00
V2	stall	spi_host_status_stall	33.933m	1.000s	48	50	96.00
V2	Idlecsbactive	spi_host_idlecsbactive	57.000s	18.087ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	45.000s	1.695ms	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	18.492us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	24.832us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	274.695us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	274.695us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	51.497us	5	5	100.00
		spi_host_csr_rw	5.000s	52.151us	20	20	100.00
		spi_host_csr_aliasing	5.000s	80.507us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	136.702us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	51.497us	5	5	100.00
		spi_host_csr_rw	5.000s	52.151us	20	20	100.00
		spi_host_csr_aliasing	5.000s	80.507us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	136.702us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	303.707us	20	20	100.00
		spi_host_sec_cm	5.000s	139.734us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	303.707us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.833m	12.643ms	10	10	100.00
		TOTAL			838	840	99.76

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.26	96.78	93.27	98.69	94.36	88.02	100.00	97.27	90.42

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 5.spi_host_status_stall.80123867019308761079587434645344467444362696623558836929388603174363722440159
    Line 1442, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/5.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

Test spi_host_status_stall has 1 failures.

31.spi_host_status_stall.10162955201147071750897479569774712571940016460240932041787295123553269062016
Line 1287, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/31.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 5937363519 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 5937363519 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=5937364000 ps
  UVM_INFO @ 5937363519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---