SRAM_CTRL/MAIN Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.605m	1.004ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.090s	25.295us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.230s	100.038us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.740s	528.245us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.200s	63.381us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.680s	374.709us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.230s	100.038us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	63.381us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.849m	76.834ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.234m	104.690ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.264m	402.556ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.350m	6.667ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	42.287m	343.714ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.651m	306.279ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.975m	19.209ms	50	50	100.00
V2	executable	sram_ctrl_executable	28.519m	87.344ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.743m	1.356ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.031m	113.333ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.795m	801.927us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.723m	3.264ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.790m	3.380ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.637m	50.482ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.220s	1.458ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.196h	782.828ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.740s	26.578us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.330s	1.112ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.330s	1.112ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.090s	25.295us	5	5	100.00
		sram_ctrl_csr_rw	2.230s	100.038us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	63.381us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.310s	22.293us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.090s	25.295us	5	5	100.00
		sram_ctrl_csr_rw	2.230s	100.038us	20	20	100.00
		sram_ctrl_csr_aliasing	2.200s	63.381us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.310s	22.293us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.262m	14.419ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.750s	2.137us	0	5	0.00
		sram_ctrl_tl_intg_err	5.480s	596.169us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.750s	2.137us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.480s	596.169us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.637m	50.482ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.637m	50.482ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.230s	100.038us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	28.519m	87.344ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	28.519m	87.344ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	28.519m	87.344ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.975m	19.209ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.570s	8.309ms	46	50	92.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.262m	14.419ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.630s	2.749ms	44	50	88.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.605m	1.004ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.605m	1.004ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	28.519m	87.344ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.750s	2.137us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.975m	19.209ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.750s	2.137us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.750s	2.137us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.605m	1.004ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.750s	2.137us	0	5	0.00
V2S		TOTAL			130	145	89.66
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.650m	13.124ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1175	1190	98.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.06	99.28	93.01	85.18	100.00	98.03	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 6 failures:

  • Test sram_ctrl_readback_err has 6 failures.

    • 3.sram_ctrl_readback_err.114434904771782202630966012260662819248608121206806902070906660998560915426327
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1347148403 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x64) != exp (0xb)
        UVM_INFO @ 1347148403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_readback_err.20525947980652157877599057773856688395452261536247441588176739200837898505693
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/7.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 659692266 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x20) != exp (0x13)
        UVM_INFO @ 659692266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• Offending 'reqfifo_rvalid' has 4 failures:

  • Test sram_ctrl_mubi_enc_err has 4 failures.

    • 8.sram_ctrl_mubi_enc_err.95197514025228495550477243020729035314697344139438191019625183272444088433949
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2630483506 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2630483506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 16.sram_ctrl_mubi_enc_err.9926198392584518673363501030416611314383754711768977405572004478687799323856
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/16.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1378411187 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1378411187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 2.sram_ctrl_sec_cm.95566553645280596237081650167976590618848218311583805936324407483912008152241
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9635453 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9635453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.15756320742203377303851712001228344345226738061316646897345928266607277730055
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7538526 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7538526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.62132678952704548496944661402847086533889620692985261645184225061174029302269
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2137478 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2137478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.96107153954103139031584533822855386140591258376101993456328046311593715141367
      Line 101, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === ((pend_req[d2h.d_source].opcode == Get) ? AccessAckData : AccessAck))'
        UVM_ERROR @   8326078 ps: (tlul_assert.sv:273) [ASSERT FAILED] respOpcode_A
        UVM_INFO @   8326078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---