SRAM_CTRL/RET Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.429m	719.234us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.070s	17.643us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.140s	14.567us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.770s	822.506us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.120s	36.883us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.950s	160.276us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.140s	14.567us	20	20	100.00
		sram_ctrl_csr_aliasing	2.120s	36.883us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.800s	4.090ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.210s	2.486ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	23.416m	34.252ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.941m	14.317ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.550m	5.411ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	17.966m	15.668ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.790s	809.936us	50	50	100.00
V2	executable	sram_ctrl_executable	21.906m	24.088ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.856m	2.922ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.352m	21.768ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.481m	1.081ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.498m	308.415us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.688m	669.962us	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.338m	16.416ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.310s	31.361us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.120h	75.232ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.170s	39.592us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.320s	478.048us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.320s	478.048us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.070s	17.643us	5	5	100.00
		sram_ctrl_csr_rw	2.140s	14.567us	20	20	100.00
		sram_ctrl_csr_aliasing	2.120s	36.883us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.230s	41.496us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.070s	17.643us	5	5	100.00
		sram_ctrl_csr_rw	2.140s	14.567us	20	20	100.00
		sram_ctrl_csr_aliasing	2.120s	36.883us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.230s	41.496us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.800s	3.521ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.110s	8.312us	0	5	0.00
		sram_ctrl_tl_intg_err	4.180s	680.111us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.110s	8.312us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.180s	680.111us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.338m	16.416ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.338m	16.416ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.140s	14.567us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.906m	24.088ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.906m	24.088ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.906m	24.088ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.790s	809.936us	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.570s	100.327us	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.800s	3.521ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.650s	148.059us	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.429m	719.234us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.429m	719.234us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.906m	24.088ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.110s	8.312us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.790s	809.936us	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.110s	8.312us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.110s	8.312us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.429m	719.234us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.110s	8.312us	0	5	0.00
V2S		TOTAL			124	145	85.52
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.081m	4.579ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1169	1190	98.24

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.26	93.01	85.10	100.00	97.99	98.58	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 11 failures:

  • Test sram_ctrl_readback_err has 11 failures.

    • 4.sram_ctrl_readback_err.57899419071296764739954350751618079672583100183745887022267639411509779416483
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 117713667 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x67) != exp (0x41)
        UVM_INFO @ 117713667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.sram_ctrl_readback_err.62195226964000683382064138472114813706365224623539952943161551467016463828831
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  30400461 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x1b) != exp (0x6e)
        UVM_INFO @  30400461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• Offending 'reqfifo_rvalid' has 5 failures:

  • Test sram_ctrl_mubi_enc_err has 5 failures.

    • 13.sram_ctrl_mubi_enc_err.72911829265026801551116737968272566672225373338141677065422176942429800325858
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/13.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 122855403 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 122855403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 25.sram_ctrl_mubi_enc_err.38485405181905585567532173949257417709997009910988528338371865102161647860720
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/25.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  65836911 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  65836911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 1.sram_ctrl_sec_cm.88474002928959587490101920898990200137859911487886730488387969603940787455971
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8311562 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8311562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.14819427862500762375538989749176994362011354709028348019872527983205987851735
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3108539 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3108539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.50558444454991171548469098609270373149301310378461202412241027923565342821847
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4448924 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4448924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 3.sram_ctrl_sec_cm.217580371000269990814770938433184090649159883386127113631573355790690390348
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   2857411 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   2857411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---