UART Simulation Results

Friday May 30 2025 17:37:41 UTC

GitHub Revision: 53e8d55

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	58.850s	11.097ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.230s	49.604us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.340s	11.320us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	4.420s	486.357us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.600s	25.763us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.850s	22.580us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.340s	11.320us	20	20	100.00
		uart_csr_aliasing	2.600s	25.763us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.992m	102.991ms	50	50	100.00
V2	parity	uart_smoke	58.850s	11.097ms	50	50	100.00
		uart_tx_rx	2.992m	102.991ms	50	50	100.00
V2	parity_error	uart_intr	10.787m	345.053ms	50	50	100.00
		uart_rx_parity_err	7.081m	199.546ms	50	50	100.00
V2	watermark	uart_tx_rx	2.992m	102.991ms	50	50	100.00
		uart_intr	10.787m	345.053ms	50	50	100.00
V2	fifo_full	uart_fifo_full	6.869m	103.314ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.207m	174.641ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.490m	205.367ms	298	300	99.33
V2	rx_frame_err	uart_intr	10.787m	345.053ms	50	50	100.00
V2	rx_break_err	uart_intr	10.787m	345.053ms	50	50	100.00
V2	rx_timeout	uart_intr	10.787m	345.053ms	50	50	100.00
V2	perf	uart_perf	13.144m	18.564ms	50	50	100.00
V2	sys_loopback	uart_loopback	33.640s	10.342ms	50	50	100.00
V2	line_loopback	uart_loopback	33.640s	10.342ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.995m	174.233ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.907m	50.749ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	27.710s	7.081ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.178m	6.755ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	14.455m	113.343ms	49	50	98.00
V2	stress_all	uart_stress_all	17.740m	398.324ms	49	50	98.00
V2	alert_test	uart_alert_test	2.150s	68.415us	50	50	100.00
V2	intr_test	uart_intr_test	2.340s	69.376us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.680s	83.002us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.680s	83.002us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.230s	49.604us	5	5	100.00
		uart_csr_rw	2.340s	11.320us	20	20	100.00
		uart_csr_aliasing	2.600s	25.763us	5	5	100.00
		uart_same_csr_outstanding	2.440s	49.714us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.230s	49.604us	5	5	100.00
		uart_csr_rw	2.340s	11.320us	20	20	100.00
		uart_csr_aliasing	2.600s	25.763us	5	5	100.00
		uart_same_csr_outstanding	2.440s	49.714us	20	20	100.00
V2		TOTAL			1086	1090	99.63
V2S	tl_intg_err	uart_sec_cm	2.400s	126.419us	5	5	100.00
		uart_tl_intg_err	3.150s	128.713us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.150s	128.713us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.100m	22.473ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1314	1320	99.55

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.84	99.48	98.25	91.55	--	98.14	100.00	99.62

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 4 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 6.uart_stress_all_with_rand_reset.55490352426193564376532479769236560226101289618626135545643109067173571346981
      Line 72, in log /nightly/runs/scratch/master/uart-sim-vcs/6.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @   3946608 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @  92841019 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/189
        UVM_INFO @ 185777032 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/189
        UVM_INFO @ 328796791 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 1/10
      

  • Test uart_fifo_reset has 2 failures.

    • 25.uart_fifo_reset.101332468043266133933068391510664918661601720625483582049088532299335171149767
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/25.uart_fifo_reset/latest/run.log

        UVM_ERROR @   1033082 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 1567991111 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6
        UVM_INFO @ 12846686903 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6
        UVM_INFO @ 95488573958 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6
        UVM_INFO @ 104732433401 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6
      

    • 48.uart_fifo_reset.18517151979136098626333077184980092049466295865649091650874409557792437257138
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/48.uart_fifo_reset/latest/run.log

        UVM_ERROR @   4023710 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 2441023710 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/10
        UVM_INFO @ 3771383710 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/10
        UVM_INFO @ 28724623710 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/10
        UVM_INFO @ 30564383710 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/10
      

  • Test uart_stress_all has 1 failures.

    • 38.uart_stress_all.20118077760408676331388053493130031265545256128450468025152279543478743837177
      Line 113, in log /nightly/runs/scratch/master/uart-sim-vcs/38.uart_stress_all/latest/run.log

        UVM_ERROR @ 358977886325 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 394285460450 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/5
        UVM_INFO @ 407185230314 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/5
        UVM_INFO @ 407540566490 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/5
        UVM_INFO @ 423303067589 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/5
      

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

  • Test uart_long_xfer_wo_dly has 1 failures.

    • 6.uart_long_xfer_wo_dly.87362138131829686294334011851185023797725586436313924917898979006131341141947
      Line 74, in log /nightly/runs/scratch/master/uart-sim-vcs/6.uart_long_xfer_wo_dly/latest/run.log

        UVM_ERROR @ 93674536639 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 93786890479 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 93876891199 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 94269717871 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
        UVM_ERROR @ 95798259511 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
      

• UVM_ERROR (cip_base_vseq.sv:928) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 57.uart_stress_all_with_rand_reset.73205591891426378391164926404477921415926021325570706622061873066119492659110
      Line 113, in log /nightly/runs/scratch/master/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1121192668 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1121199789 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1121199789 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 5/10
        UVM_INFO @ 1121202668 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1