AES/MASKED Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	32.000s	155.893us	1	1	100.00
V1	smoke	aes_smoke	14.000s	115.323us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	208.568us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	158.969us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	2.810ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	774.829us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	182.896us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	158.969us	20	20	100.00
		aes_csr_aliasing	6.000s	774.829us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	115.323us	50	50	100.00
		aes_config_error	23.000s	1.141ms	50	50	100.00
		aes_stress	16.000s	639.605us	50	50	100.00
V2	key_length	aes_smoke	14.000s	115.323us	50	50	100.00
		aes_config_error	23.000s	1.141ms	50	50	100.00
		aes_stress	16.000s	639.605us	50	50	100.00
V2	back2back	aes_stress	16.000s	639.605us	50	50	100.00
		aes_b2b	42.000s	811.618us	50	50	100.00
V2	backpressure	aes_stress	16.000s	639.605us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	115.323us	50	50	100.00
		aes_config_error	23.000s	1.141ms	50	50	100.00
		aes_stress	16.000s	639.605us	50	50	100.00
		aes_alert_reset	29.000s	1.629ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	30.000s	59.507us	50	50	100.00
		aes_config_error	23.000s	1.141ms	50	50	100.00
		aes_alert_reset	29.000s	1.629ms	50	50	100.00
V2	trigger_clear_test	aes_clear	29.000s	4.932ms	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	3.883m	16.865ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	29.000s	1.629ms	50	50	100.00
V2	stress	aes_stress	16.000s	639.605us	50	50	100.00
V2	sideload	aes_stress	16.000s	639.605us	50	50	100.00
		aes_sideload	12.000s	629.558us	50	50	100.00
V2	deinitialization	aes_deinit	46.000s	849.208us	50	50	100.00
V2	stress_all	aes_stress_all	4.367m	19.793ms	9	10	90.00
V2	alert_test	aes_alert_test	6.000s	130.211us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	680.644us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	680.644us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	208.568us	5	5	100.00
		aes_csr_rw	6.000s	158.969us	20	20	100.00
		aes_csr_aliasing	6.000s	774.829us	5	5	100.00
		aes_same_csr_outstanding	5.000s	205.176us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	208.568us	5	5	100.00
		aes_csr_rw	6.000s	158.969us	20	20	100.00
		aes_csr_aliasing	6.000s	774.829us	5	5	100.00
		aes_same_csr_outstanding	5.000s	205.176us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	15.000s	607.956us	50	50	100.00
V2S	fault_inject	aes_fi	21.000s	2.704ms	50	50	100.00
		aes_control_fi	47.000s	10.006ms	275	300	91.67
		aes_cipher_fi	45.000s	10.006ms	338	350	96.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	135.053us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	135.053us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	135.053us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	135.053us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	974.913us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.451ms	5	5	100.00
		aes_tl_intg_err	8.000s	354.496us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	354.496us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	29.000s	1.629ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	135.053us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	115.323us	50	50	100.00
		aes_stress	16.000s	639.605us	50	50	100.00
		aes_alert_reset	29.000s	1.629ms	50	50	100.00
		aes_core_fi	28.000s	10.121ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	135.053us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	21.000s	79.182us	50	50	100.00
		aes_stress	16.000s	639.605us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	16.000s	639.605us	50	50	100.00
		aes_sideload	12.000s	629.558us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	21.000s	79.182us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	21.000s	79.182us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	21.000s	79.182us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	21.000s	79.182us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	21.000s	79.182us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	16.000s	639.605us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	16.000s	639.605us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	21.000s	2.704ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	21.000s	2.704ms	50	50	100.00
		aes_control_fi	47.000s	10.006ms	275	300	91.67
		aes_cipher_fi	45.000s	10.006ms	338	350	96.57
		aes_ctr_fi	10.000s	517.239us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	21.000s	2.704ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	21.000s	2.704ms	50	50	100.00
		aes_control_fi	47.000s	10.006ms	275	300	91.67
		aes_cipher_fi	45.000s	10.006ms	338	350	96.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	10.006ms	338	350	96.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	21.000s	2.704ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	21.000s	2.704ms	50	50	100.00
		aes_control_fi	47.000s	10.006ms	275	300	91.67
		aes_ctr_fi	10.000s	517.239us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	21.000s	2.704ms	50	50	100.00
		aes_control_fi	47.000s	10.006ms	275	300	91.67
		aes_cipher_fi	45.000s	10.006ms	338	350	96.57
		aes_ctr_fi	10.000s	517.239us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	29.000s	1.629ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	21.000s	2.704ms	50	50	100.00
		aes_control_fi	47.000s	10.006ms	275	300	91.67
		aes_cipher_fi	45.000s	10.006ms	338	350	96.57
		aes_ctr_fi	10.000s	517.239us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	21.000s	2.704ms	50	50	100.00
		aes_control_fi	47.000s	10.006ms	275	300	91.67
		aes_cipher_fi	45.000s	10.006ms	338	350	96.57
		aes_ctr_fi	10.000s	517.239us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	21.000s	2.704ms	50	50	100.00
		aes_control_fi	47.000s	10.006ms	275	300	91.67
		aes_ctr_fi	10.000s	517.239us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	21.000s	2.704ms	50	50	100.00
		aes_control_fi	47.000s	10.006ms	275	300	91.67
		aes_cipher_fi	45.000s	10.006ms	338	350	96.57
V2S		TOTAL			947	985	96.14
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	23.000s	1.606ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1552	1602	96.88

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	98.60	96.45	99.44	95.51	97.99	97.78	98.96	98.19

Failure Buckets

Job timed out after * minutes has 15 failures:
- Test aes_control_fi has 14 failures.
  - 6.aes_control_fi.82344804765285509871685117317352124501838533632091661251452403802788990302890
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 7.aes_control_fi.34148937333502232034539560814003039280034567938885829356159579369277262506101
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 1 failures.
  - 188.aes_cipher_fi.39764323940879007304504753312126573688890387062589013460634404376385783512186
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/188.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 31.aes_cipher_fi.104383361374190376846946032718495645581147374889925595660184386116957369374860
    Line 141, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014174515 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014174515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 41.aes_cipher_fi.38260976625257998753093111727502836245006475139386096080646765917162921416680
    Line 140, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/41.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006421577 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006421577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 39.aes_control_fi.91516454311825195348141893585783823758572696622355517282267021704847943220957
    Line 143, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011313722 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011313722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 65.aes_control_fi.37575706936368829582914073010790743108939062449598481327037488631547578342961
    Line 131, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/65.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003072818 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003072818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.97247639392590804627888745629490302207857069563400111923211069141808821930286
Line 390, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 691644854 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 691644854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.93685107152306520315293916197740048768804315257667669311634625453076444151598
Line 462, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1760102390 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1760102390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.75087353599646468045909056621164934986576827690090387474589895260372605216116
    Line 185, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 115632685 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 115632685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.aes_stress_all_with_rand_reset.30461630166666545312389600946007547297583869819821057770851561218793838587972
    Line 479, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1353824522 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1353824522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

4.aes_stress_all.11975522818867622609305916771506367421561092867533365991044555664545835613337
Line 111056, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 1199007973 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 1198966306 PS)
  UVM_ERROR @ 1199007973 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 1199007973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.14233954291268409449495163332578621022327813848264621076857625780831411741792
    Line 472, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 441795501 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 441795501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 10.aes_core_fi.53985943504716374668446952267325006979693798482754215235042044901039208909774
    Line 140, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10120987121 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10120987121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 36.aes_clear.40075281945113384118497357667843094918933116412410559477038498593187288264707
    Line 1808, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/36.aes_clear/latest/run.log
```
  UVM_FATAL @  12885142 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
           TEST FAILED MESSAGES DID NOT MATCH

                 0 ed 	 12 	 59 	 0
                 1 9c 	 19 	 e1 	 0
```