AES/UNMASKED Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	9.000s	68.492us	1	1	100.00
V1	smoke	aes_smoke	6.000s	60.941us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	56.503us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	86.332us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	985.294us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	166.745us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	143.741us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	86.332us	20	20	100.00
		aes_csr_aliasing	6.000s	166.745us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	60.941us	50	50	100.00
		aes_config_error	7.000s	1.012ms	50	50	100.00
		aes_stress	7.000s	245.181us	50	50	100.00
V2	key_length	aes_smoke	6.000s	60.941us	50	50	100.00
		aes_config_error	7.000s	1.012ms	50	50	100.00
		aes_stress	7.000s	245.181us	50	50	100.00
V2	back2back	aes_stress	7.000s	245.181us	50	50	100.00
		aes_b2b	11.000s	693.993us	50	50	100.00
V2	backpressure	aes_stress	7.000s	245.181us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	60.941us	50	50	100.00
		aes_config_error	7.000s	1.012ms	50	50	100.00
		aes_stress	7.000s	245.181us	50	50	100.00
		aes_alert_reset	6.000s	85.370us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	68.541us	50	50	100.00
		aes_config_error	7.000s	1.012ms	50	50	100.00
		aes_alert_reset	6.000s	85.370us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	111.151us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	716.468us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	85.370us	50	50	100.00
V2	stress	aes_stress	7.000s	245.181us	50	50	100.00
V2	sideload	aes_stress	7.000s	245.181us	50	50	100.00
		aes_sideload	7.000s	149.482us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	679.223us	50	50	100.00
V2	stress_all	aes_stress_all	6.950m	10.283ms	9	10	90.00
V2	alert_test	aes_alert_test	6.000s	94.097us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	106.308us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	106.308us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	56.503us	5	5	100.00
		aes_csr_rw	5.000s	86.332us	20	20	100.00
		aes_csr_aliasing	6.000s	166.745us	5	5	100.00
		aes_same_csr_outstanding	6.000s	134.104us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	56.503us	5	5	100.00
		aes_csr_rw	5.000s	86.332us	20	20	100.00
		aes_csr_aliasing	6.000s	166.745us	5	5	100.00
		aes_same_csr_outstanding	6.000s	134.104us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	7.000s	185.309us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	230.479us	50	50	100.00
		aes_control_fi	33.000s	10.003ms	281	300	93.67
		aes_cipher_fi	28.000s	10.004ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	274.145us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	274.145us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	274.145us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	274.145us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	1.097ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	858.398us	5	5	100.00
		aes_tl_intg_err	6.000s	178.225us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	178.225us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	85.370us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	274.145us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	60.941us	50	50	100.00
		aes_stress	7.000s	245.181us	50	50	100.00
		aes_alert_reset	6.000s	85.370us	50	50	100.00
		aes_core_fi	1.967m	10.018ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	274.145us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	262.733us	50	50	100.00
		aes_stress	7.000s	245.181us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	245.181us	50	50	100.00
		aes_sideload	7.000s	149.482us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	262.733us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	262.733us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	262.733us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	262.733us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	262.733us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	245.181us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	245.181us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	230.479us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	230.479us	50	50	100.00
		aes_control_fi	33.000s	10.003ms	281	300	93.67
		aes_cipher_fi	28.000s	10.004ms	326	350	93.14
		aes_ctr_fi	6.000s	54.260us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	230.479us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	230.479us	50	50	100.00
		aes_control_fi	33.000s	10.003ms	281	300	93.67
		aes_cipher_fi	28.000s	10.004ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	28.000s	10.004ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	230.479us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	230.479us	50	50	100.00
		aes_control_fi	33.000s	10.003ms	281	300	93.67
		aes_ctr_fi	6.000s	54.260us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	230.479us	50	50	100.00
		aes_control_fi	33.000s	10.003ms	281	300	93.67
		aes_cipher_fi	28.000s	10.004ms	326	350	93.14
		aes_ctr_fi	6.000s	54.260us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	85.370us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	230.479us	50	50	100.00
		aes_control_fi	33.000s	10.003ms	281	300	93.67
		aes_cipher_fi	28.000s	10.004ms	326	350	93.14
		aes_ctr_fi	6.000s	54.260us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	230.479us	50	50	100.00
		aes_control_fi	33.000s	10.003ms	281	300	93.67
		aes_cipher_fi	28.000s	10.004ms	326	350	93.14
		aes_ctr_fi	6.000s	54.260us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	230.479us	50	50	100.00
		aes_control_fi	33.000s	10.003ms	281	300	93.67
		aes_ctr_fi	6.000s	54.260us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	230.479us	50	50	100.00
		aes_control_fi	33.000s	10.003ms	281	300	93.67
		aes_cipher_fi	28.000s	10.004ms	326	350	93.14
V2S		TOTAL			938	985	95.23
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	21.000s	729.776us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.31	97.67	94.75	98.84	93.34	97.99	93.33	98.65	98.39

Failure Buckets

Job timed out after * minutes has 25 failures:
- Test aes_control_fi has 11 failures.
  - 14.aes_control_fi.84581060676331637842726046150873221260271533853777543272827883493160912601419
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 19.aes_control_fi.21226537319002306400902598997988025716871860572106103378170104537092145103664
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 14 failures.
  - 30.aes_cipher_fi.61815039445411604123211565754070698107692555852050264734199894498318503532635
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 93.aes_cipher_fi.19854875031121671141000245374778324032785164722113303956815043490186469999012
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/93.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 3.aes_cipher_fi.27089692085551068067119577378872749191724060936128739109068401906466666477502
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008337988 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008337988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 26.aes_cipher_fi.8382612412874125575582641581073286553832149432846745165127841453734930729105
    Line 144, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003738205 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003738205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 12.aes_control_fi.9963005546493460747692777850300169873996676365047094234013455836028993596603
    Line 144, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10013922816 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013922816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 125.aes_control_fi.35535462405858014160506014990561168273582655746250461055231583812825210997246
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/125.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005439538 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005439538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.93022018647856818398762481368932412740057334807005017347275025356384358952563
Line 634, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 620876236 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 620876236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.8778990083778072727252037380290580733023088582100081899345891697017197075131
Line 1246, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 729776138 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 729776138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.66027625021321937175412317198700572993698699750950491744313423785838199950800
    Line 565, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 915774211 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 915774211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.aes_stress_all_with_rand_reset.81342144366741277618856399665954625794588329450393490670599035571395349596141
    Line 431, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 431574135 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 431574135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 29.aes_core_fi.24848724548105735307511069400198111307756912745784033609526257017718655815986
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011840739 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011840739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 58.aes_core_fi.23336284627264220168056283229786121993412523265146606685144107685613259354708
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/58.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017709950 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017709950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.108710186274381457172534491659377299634915425944722241311879761082775442384397
    Line 158, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  73140820 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  73140820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=92) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 6.aes_stress_all.29112806411197743715730661784577864170754247847491049745551365290744320464208
    Line 4910333, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 10283185862 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x94651a84, Comparison=CompareOpEq, exp_data=0x1, call_count=92)
  UVM_INFO @ 10283185862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 21.aes_clear.73361665076489414224855117431613157680942406168956805039231527842397561670043
    Line 1193, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/21.aes_clear/latest/run.log
```
  UVM_FATAL @  33011804 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
           TEST FAILED MESSAGES DID NOT MATCH

                 0 96 	 9c 	 95 	 0
                 1 00 	 a0 	 ad 	 0
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 32.aes_core_fi.39144737288378972990577431775380290793929670260926898264366673386055354737455
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008090547 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008090547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 35.aes_core_fi.42988530330427698391651458686943057020268150163990471884807138804861536105091
    Line 132, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018057558 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x6e070784, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10018057558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```