AON_TIMER Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.650s	711.331us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.660s	990.350us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	3.430s	463.678us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	25.730s	13.884ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	3.840s	596.852us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	3.300s	501.130us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	3.430s	463.678us	20	20	100.00
		aon_timer_csr_aliasing	3.840s	596.852us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	2.690s	271.792us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.560s	281.545us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	1.852m	62.041ms	15	15	100.00
V2	jump	aon_timer_jump	3.370s	683.442us	5	5	100.00
V2	stress_all	aon_timer_stress_all	3.611m	106.282ms	15	15	100.00
V2	alert_test	aon_timer_alert_test	3.400s	517.071us	50	50	100.00
V2	intr_test	aon_timer_intr_test	3.140s	455.284us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	4.170s	434.385us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	4.170s	434.385us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.660s	990.350us	5	5	100.00
		aon_timer_csr_rw	3.430s	463.678us	20	20	100.00
		aon_timer_csr_aliasing	3.840s	596.852us	5	5	100.00
		aon_timer_same_csr_outstanding	16.830s	3.403ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.660s	990.350us	5	5	100.00
		aon_timer_csr_rw	3.430s	463.678us	20	20	100.00
		aon_timer_csr_aliasing	3.840s	596.852us	5	5	100.00
		aon_timer_same_csr_outstanding	16.830s	3.403ms	20	20	100.00
V2		TOTAL			175	175	100.00
V2S	tl_intg_err	aon_timer_sec_cm	6.860s	4.340ms	5	5	100.00
		aon_timer_tl_intg_err	19.330s	8.551ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	19.330s	8.551ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	max_threshold	aon_timer_smoke_max_thold	2.660s	578.687us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	3.370s	696.409us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	14.830s	3.768ms	5	5	100.00
V3	custom_intr	aon_timer_custom_intr	3.330s	550.792us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	24.240s	4.232ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	55.360s	47.889ms	15	15	100.00
V3		TOTAL			45	45	100.00
		TOTAL			315	315	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.29	99.09	99.05	100.00	--	98.56	99.05	100.00