CSRNG Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	280.467us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	22.211us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	40.520us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	26.000s	1.191ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	253.124us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	74.303us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	40.520us	20	20	100.00
		csrng_csr_aliasing	8.000s	253.124us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	26.000s	1.386ms	164	200	82.00
V2	alerts	csrng_alert	1.083m	5.003ms	500	500	100.00
V2	err	csrng_err	7.000s	43.361us	447	500	89.40
V2	cmds	csrng_cmds	13.550m	68.747ms	50	50	100.00
V2	life cycle	csrng_cmds	13.550m	68.747ms	50	50	100.00
V2	stress_all	csrng_stress_all	14.317m	57.451ms	49	50	98.00
V2	intr_test	csrng_intr_test	6.000s	164.886us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	63.472us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	591.086us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	591.086us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	22.211us	5	5	100.00
		csrng_csr_rw	6.000s	40.520us	20	20	100.00
		csrng_csr_aliasing	8.000s	253.124us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	386.648us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	22.211us	5	5	100.00
		csrng_csr_rw	6.000s	40.520us	20	20	100.00
		csrng_csr_aliasing	8.000s	253.124us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	386.648us	20	20	100.00
V2		TOTAL			1350	1440	93.75
V2S	tl_intg_err	csrng_sec_cm	9.000s	78.362us	5	5	100.00
		csrng_tl_intg_err	23.000s	2.114ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	115.085us	50	50	100.00
		csrng_csr_rw	6.000s	40.520us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.083m	5.003ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	14.317m	57.451ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
		csrng_sec_cm	9.000s	78.362us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
		csrng_sec_cm	9.000s	78.362us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
		csrng_sec_cm	9.000s	78.362us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
		csrng_sec_cm	9.000s	78.362us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
		csrng_sec_cm	9.000s	78.362us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
		csrng_sec_cm	9.000s	78.362us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
		csrng_sec_cm	9.000s	78.362us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.083m	5.003ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
V2S	sec_cm_constants_lc_gated	csrng_stress_all	14.317m	57.451ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.083m	5.003ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	23.000s	2.114ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
		csrng_sec_cm	9.000s	78.362us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
		csrng_sec_cm	9.000s	78.362us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	26.000s	1.386ms	164	200	82.00
		csrng_err	7.000s	43.361us	447	500	89.40
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	3.467m	13.323ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1530	1630	93.87

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.52	98.51	96.38	99.83	97.42	91.96	88.00	95.96	89.52

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_control_fsm.sv,452): Assertion u_state_regs_A has failed has 54 failures:

Test csrng_intr has 21 failures.

16.csrng_intr.91897717387513381149667343288495282254828027727027554600938766089136079799734
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/16.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 317460239 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[1].gen_fsm_p.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @ 317460239 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 317460239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.csrng_intr.113863264951863034697729870610330013287897422576940322517866774269497704270522
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/18.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 312456767 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @ 312456767 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 312456767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 19 more failures.

Test csrng_err has 33 failures.

20.csrng_err.63623237369381149075125934471603053895771819620801349642630472815440707865026
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/20.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 2042775 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @   2042775 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   2042775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.csrng_err.10171416029892244419679038187791342715050925072969368689123307189484319488161
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/31.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_control_fsm.sv,452): (time 2399576 PS) Assertion tb.dut.u_csrng_core.u_csrng_block_encrypt.u_aes_cipher_core.u_aes_cipher_control.gen_fsm[2].gen_fsm_n.u_aes_cipher_control_fsm_i.u_aes_cipher_control_fsm.u_state_regs_A has failed
  UVM_ERROR @   2399576 ps: (aes_cipher_control_fsm.sv:452) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   2399576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 31 more failures.

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 0.csrng_stress_all_with_rand_reset.40809131569681983192273496431187271493510253398792529817237429495348109202204
    Line 102, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2444929169 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2444929169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.66749541725677178413623761216062952020170154420115597261843671391370789059988
    Line 105, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1055667729 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1055667729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,188): Assertion u_blk_enc_state_regs_A has failed has 9 failures:

Test csrng_err has 6 failures.

1.csrng_err.108880850124341262907534796840606608836464823609983277977639511355879062121797
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 4765730 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @   4765730 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @   4765730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

139.csrng_err.59029637863805571268211029710586312794849380314965496768840165607234446570514
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/139.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 30823163 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @  30823163 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @  30823163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test csrng_intr has 3 failures.

61.csrng_intr.68113601845873815519219036761701831890960791688425897619327578309773935864704
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/61.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 362688899 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @ 362688899 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @ 362688899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

107.csrng_intr.94425671153895560284118528998367813606692097493022340912981179060401875376753
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/107.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,188): (time 343008484 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_blk_enc_state_regs_A has failed
  UVM_ERROR @ 343008484 ps: (csrng_ctr_drbg_upd.sv:188) [ASSERT FAILED] u_blk_enc_state_regs_A
  UVM_INFO @ 343008484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_main_sm.sv,35): Assertion u_state_regs_A has failed has 9 failures:

Test csrng_intr has 4 failures.

42.csrng_intr.11522800788087083723531690853783376398936620579058974871585687988072357165486
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/42.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 272243996 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @ 272243996 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 272243996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.csrng_intr.76048696058320217321304528877132158790063667558025263697835678781195559116994
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/46.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 158770898 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @ 158770898 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 158770898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test csrng_err has 5 failures.

65.csrng_err.75173015929469403635561700890015907559482912901602452629256285162772024347967
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/65.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 5251174 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @   5251174 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   5251174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

70.csrng_err.83345492765397416643470037583775804543432995978406057077798304029850837630573
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/70.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_main_sm.sv,35): (time 1711563 PS) Assertion tb.dut.u_csrng_core.u_csrng_main_sm.u_state_regs_A has failed
  UVM_ERROR @   1711563 ps: (csrng_main_sm.sv:35) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   1711563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_gen.sv,222): Assertion u_state_regs_A has failed has 8 failures:

Test csrng_err has 7 failures.

61.csrng_err.17616833118538206822475273996965634839636212192679542622405277798740044460635
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/61.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 2119406 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @   2119406 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   2119406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

264.csrng_err.76243175848934601551058934421055162081232672125798639321700347127867655495588
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/264.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 6875818 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @   6875818 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @   6875818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test csrng_intr has 1 failures.

145.csrng_intr.61553066505314306118371853573591187468098180435636993297409206607898233054647
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/145.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_gen.sv,222): (time 104950030 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_gen.u_state_regs_A has failed
  UVM_ERROR @ 104950030 ps: (csrng_ctr_drbg_gen.sv:222) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 104950030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,260): Assertion u_state_regs_A has failed has 5 failures:

Test csrng_intr has 5 failures.

17.csrng_intr.83526619160474063818481703747870314187188314078747282573934996982286325776038
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/17.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,260): (time 787358871 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.u_state_regs_A has failed
  UVM_ERROR @ 787358871 ps: (csrng_cmd_stage.sv:260) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 787358871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.csrng_intr.95458610739041709966641358783693511855949190755916425631308118060442162885888
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/45.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,260): (time 158614150 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.u_state_regs_A has failed
  UVM_ERROR @ 158614150 ps: (csrng_cmd_stage.sv:260) [ASSERT FAILED] u_state_regs_A
  UVM_INFO @ 158614150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_ctr_drbg_upd.sv,222): Assertion u_outblk_state_regs_A has failed has 3 failures:

Test csrng_err has 2 failures.

13.csrng_err.90936325914160053729884206358071998792207716541439587341687586147373707675457
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/13.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 4542364 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @   4542364 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @   4542364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

286.csrng_err.96006826362293244807498468070203201951898109144825109649340269608555583351321
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/286.csrng_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 7884860 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @   7884860 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @   7884860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test csrng_intr has 1 failures.

74.csrng_intr.10407715551213246907370686228988662032370985640346405532726634066556064010391
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/74.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_ctr_drbg_upd.sv,222): (time 68888927 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd.u_outblk_state_regs_A has failed
  UVM_ERROR @  68888927 ps: (csrng_ctr_drbg_upd.sv:222) [ASSERT FAILED] u_outblk_state_regs_A
  UVM_INFO @  68888927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 35.csrng_stress_all.72619759626052937121545330263787905974520133805720371364930423683790918622253
    Line 135, in log /nightly/runs/scratch/master/csrng-sim-xcelium/35.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1402636023 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1402636023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

168.csrng_intr.81469042464470981569639037914704495153656861670844966665918566050817901519433
Line 166, in log /nightly/runs/scratch/master/csrng-sim-xcelium/168.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 157932450 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 157932450 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 157932450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---