DMA Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	12.000s	1.638ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	12.000s	1.657ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	13.000s	1.544ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	36.000s	70.241us	5	5	100.00
V1	csr_rw	dma_csr_rw	36.000s	27.851us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	40.000s	616.202us	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	39.000s	321.587us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	36.000s	40.988us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	36.000s	27.851us	20	20	100.00
		dma_csr_aliasing	39.000s	321.587us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	2.100m	18.676ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	51.083m	239.283ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	26.733m	517.511ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	33.933m	170.271ms	4	5	80.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	51.083m	239.283ms	3	3	100.00
V2	dma_abort	dma_abort	21.000s	2.073ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	3.083m	59.299ms	3	3	100.00
V2	intr_test	dma_intr_test	36.000s	22.055us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	38.000s	594.427us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	38.000s	594.427us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	36.000s	70.241us	5	5	100.00
		dma_csr_rw	36.000s	27.851us	20	20	100.00
		dma_csr_aliasing	39.000s	321.587us	5	5	100.00
		dma_same_csr_outstanding	36.000s	293.188us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	36.000s	70.241us	5	5	100.00
		dma_csr_rw	36.000s	27.851us	20	20	100.00
		dma_csr_aliasing	39.000s	321.587us	5	5	100.00
		dma_same_csr_outstanding	36.000s	293.188us	20	20	100.00
V2		TOTAL			113	114	99.12
V2S	dma_illegal_addr_range	dma_mem_enabled	43.000s	403.282us	5	5	100.00
		dma_generic_stress	33.933m	170.271ms	4	5	80.00
		dma_handshake_stress	51.083m	239.283ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	37.000s	94.553us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.950m	30.728ms	5	5	100.00
		dma_longer_transfer	9.000s	957.935us	5	5	100.00
		TOTAL			303	304	99.67

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.60	96.97	95.19	96.28	95.97	77.31	82.76	97.77	42.59

Failure Buckets

• Job timed out after * minutes has 1 failures:
  • Test dma_generic_stress has 1 failures.

    • 4.dma_generic_stress.101633996969261815340054160223230720985463562899475210798424087494960984542420
      Log /nightly/runs/scratch/master/dma-sim-xcelium/4.dma_generic_stress/latest/run.log

        Job timed out after 60 minutes