EDN Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.540s 36.271us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.420s 65.762us 5 5 100.00
V1 csr_rw edn_csr_rw 2.510s 16.114us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.710s 346.413us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.900s 39.578us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 3.120s 35.456us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.510s 16.114us 20 20 100.00
edn_csr_aliasing 2.900s 39.578us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 6.560s 356.724us 300 300 100.00
V2 csrng_commands edn_genbits 6.560s 356.724us 300 300 100.00
V2 genbits edn_genbits 6.560s 356.724us 300 300 100.00
V2 interrupts edn_intr 2.760s 22.703us 50 50 100.00
V2 alerts edn_alert 2.890s 29.057us 200 200 100.00
V2 errs edn_err 2.960s 29.967us 100 100 100.00
V2 disable edn_disable 2.460s 19.220us 50 50 100.00
edn_disable_auto_req_mode 3.030s 400.930us 50 50 100.00
V2 stress_all edn_stress_all 8.660s 1.117ms 50 50 100.00
V2 intr_test edn_intr_test 2.510s 11.883us 50 50 100.00
V2 alert_test edn_alert_test 3.170s 77.816us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.260s 111.924us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.260s 111.924us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.420s 65.762us 5 5 100.00
edn_csr_rw 2.510s 16.114us 20 20 100.00
edn_csr_aliasing 2.900s 39.578us 5 5 100.00
edn_same_csr_outstanding 3.160s 159.942us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.420s 65.762us 5 5 100.00
edn_csr_rw 2.510s 16.114us 20 20 100.00
edn_csr_aliasing 2.900s 39.578us 5 5 100.00
edn_same_csr_outstanding 3.160s 159.942us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 11.080s 565.440us 5 5 100.00
edn_tl_intg_err 4.810s 187.095us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.610s 18.711us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.890s 29.057us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 11.080s 565.440us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 11.080s 565.440us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 11.080s 565.440us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 11.080s 565.440us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.890s 29.057us 200 200 100.00
edn_sec_cm 11.080s 565.440us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.890s 29.057us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.810s 187.095us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.920m 19.875ms 27 50 54.00
V3 TOTAL 27 50 54.00
TOTAL 1107 1130 97.96

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.78 98.87 94.05 97.02 91.28 96.33 99.78 93.13

Failure Buckets