HMAC Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	11.760s	957.092us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.330s	102.128us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.510s	31.341us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.900s	1.281ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.100s	151.908us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.553m	247.640ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.510s	31.341us	20	20	100.00
		hmac_csr_aliasing	8.100s	151.908us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.582m	4.404ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.628m	21.002ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.564m	29.200ms	30	30	100.00
		hmac_test_sha384_vectors	9.989m	27.573ms	75	75	100.00
		hmac_test_sha512_vectors	9.888m	15.121ms	75	75	100.00
		hmac_test_hmac256_vectors	16.820s	350.459us	50	50	100.00
		hmac_test_hmac384_vectors	20.430s	1.799ms	60	60	100.00
		hmac_test_hmac512_vectors	20.430s	544.004us	75	75	100.00
V2	burst_wr	hmac_burst_wr	40.940s	2.674ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	15.778m	13.656ms	10	10	100.00
V2	error	hmac_error	1.300m	12.117ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.862m	9.057ms	10	10	100.00
V2	save_and_restore	hmac_smoke	11.760s	957.092us	10	10	100.00
		hmac_long_msg	1.582m	4.404ms	10	10	100.00
		hmac_back_pressure	1.628m	21.002ms	25	25	100.00
		hmac_datapath_stress	15.778m	13.656ms	10	10	100.00
		hmac_burst_wr	40.940s	2.674ms	50	50	100.00
		hmac_stress_all	28.961m	53.211ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	11.760s	957.092us	10	10	100.00
		hmac_long_msg	1.582m	4.404ms	10	10	100.00
		hmac_back_pressure	1.628m	21.002ms	25	25	100.00
		hmac_datapath_stress	15.778m	13.656ms	10	10	100.00
		hmac_wipe_secret	1.862m	9.057ms	10	10	100.00
		hmac_test_sha256_vectors	4.564m	29.200ms	30	30	100.00
		hmac_test_sha384_vectors	9.989m	27.573ms	75	75	100.00
		hmac_test_sha512_vectors	9.888m	15.121ms	75	75	100.00
		hmac_test_hmac256_vectors	16.820s	350.459us	50	50	100.00
		hmac_test_hmac384_vectors	20.430s	1.799ms	60	60	100.00
		hmac_test_hmac512_vectors	20.430s	544.004us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	11.760s	957.092us	10	10	100.00
		hmac_long_msg	1.582m	4.404ms	10	10	100.00
		hmac_back_pressure	1.628m	21.002ms	25	25	100.00
		hmac_datapath_stress	15.778m	13.656ms	10	10	100.00
		hmac_burst_wr	40.940s	2.674ms	50	50	100.00
		hmac_error	1.300m	12.117ms	10	10	100.00
		hmac_wipe_secret	1.862m	9.057ms	10	10	100.00
		hmac_test_sha256_vectors	4.564m	29.200ms	30	30	100.00
		hmac_test_sha384_vectors	9.989m	27.573ms	75	75	100.00
		hmac_test_sha512_vectors	9.888m	15.121ms	75	75	100.00
		hmac_test_hmac256_vectors	16.820s	350.459us	50	50	100.00
		hmac_test_hmac384_vectors	20.430s	1.799ms	60	60	100.00
		hmac_test_hmac512_vectors	20.430s	544.004us	75	75	100.00
		hmac_stress_all	28.961m	53.211ms	50	50	100.00
V2	stress_all	hmac_stress_all	28.961m	53.211ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.150s	14.029us	50	50	100.00
V2	intr_test	hmac_intr_test	2.200s	42.787us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.840s	242.285us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.840s	242.285us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.330s	102.128us	5	5	100.00
		hmac_csr_rw	2.510s	31.341us	20	20	100.00
		hmac_csr_aliasing	8.100s	151.908us	5	5	100.00
		hmac_same_csr_outstanding	4.100s	230.793us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.330s	102.128us	5	5	100.00
		hmac_csr_rw	2.510s	31.341us	20	20	100.00
		hmac_csr_aliasing	8.100s	151.908us	5	5	100.00
		hmac_same_csr_outstanding	4.100s	230.793us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.410s	162.211us	5	5	100.00
		hmac_tl_intg_err	6.220s	1.054ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.220s	1.054ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	11.760s	957.092us	10	10	100.00
V3	stress_reset	hmac_stress_reset	9.960s	300.277us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	13.853m	55.933ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.030s	44.432us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.08	100.00	97.25	100.00	100.00	100.00	100.00	47.30