I2C Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.300m	4.112ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	39.900s	4.621ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.240s	20.454us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.320s	30.349us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	7.020s	2.351ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.240s	43.011us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.880s	128.909us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.320s	30.349us	20	20	100.00
		i2c_csr_aliasing	3.240s	43.011us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	12.290s	475.875us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	34.279m	38.793ms	12	50	24.00
V2	host_maxperf	i2c_host_perf	37.951m	49.173ms	50	50	100.00
V2	host_override	i2c_host_override	2.250s	33.667us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.084m	5.144ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.262m	9.166ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.770s	544.643us	50	50	100.00
		i2c_host_fifo_fmt_empty	24.540s	2.060ms	50	50	100.00
		i2c_host_fifo_reset_rx	13.780s	234.050us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.869m	14.346ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	43.660s	4.402ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	6.710s	152.130us	15	50	30.00
V2	target_glitch	i2c_target_glitch	12.410s	2.064ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	16.715m	61.096ms	48	50	96.00
V2	target_maxperf	i2c_target_perf	8.860s	3.830ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	59.680s	20.713ms	50	50	100.00
		i2c_target_intr_smoke	11.720s	1.302ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.580s	414.398us	50	50	100.00
		i2c_target_fifo_reset_tx	3.550s	259.072us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	17.123m	65.770ms	50	50	100.00
		i2c_target_stress_rd	59.680s	20.713ms	50	50	100.00
		i2c_target_intr_stress_wr	5.941m	23.547ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	11.300s	1.359ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	3.622m	5.327ms	43	50	86.00
V2	bad_address	i2c_target_bad_addr	11.130s	6.753ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	36.120s	10.079ms	26	50	52.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.460s	1.781ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.440s	202.174us	49	50	98.00
V2	host_mode_config_perf	i2c_host_perf	37.951m	49.173ms	50	50	100.00
		i2c_host_perf_precise	4.912m	6.134ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	43.660s	4.402ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	20.710s	1.457ms	49	50	98.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.960s	2.216ms	50	50	100.00
		i2c_target_nack_acqfull_addr	4.850s	1.055ms	50	50	100.00
		i2c_target_nack_txstretch	3.380s	571.049us	34	50	68.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	24.770s	720.769us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.540s	488.472us	50	50	100.00
V2	alert_test	i2c_alert_test	2.170s	18.509us	50	50	100.00
V2	intr_test	i2c_intr_test	2.210s	54.616us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	4.000s	166.916us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	4.000s	166.916us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.240s	20.454us	5	5	100.00
		i2c_csr_rw	2.320s	30.349us	20	20	100.00
		i2c_csr_aliasing	3.240s	43.011us	5	5	100.00
		i2c_same_csr_outstanding	2.680s	51.756us	18	20	90.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.240s	20.454us	5	5	100.00
		i2c_csr_rw	2.320s	30.349us	20	20	100.00
		i2c_csr_aliasing	3.240s	43.011us	5	5	100.00
		i2c_same_csr_outstanding	2.680s	51.756us	18	20	90.00
V2		TOTAL			1666	1792	92.97
V2S	tl_intg_err	i2c_tl_intg_err	3.570s	269.883us	20	20	100.00
		i2c_sec_cm	2.700s	78.745us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.570s	269.883us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	38.350s	3.986ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	4.200s	2.192ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	19.694m	600.000ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1846	2042	90.40

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.95	97.47	89.52	74.17	72.02	94.18	98.52	89.75

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 46 failures:

Test i2c_host_mode_toggle has 20 failures.

0.i2c_host_mode_toggle.5805803696532936461611557021681152493963609592710101246674558498635872663372
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 564785222 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @9015

3.i2c_host_mode_toggle.13008832857033001125551264140152782728529896348929905945067669880093983231829
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 374438251 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @63225

... and 18 more failures.

Test i2c_host_stress_all has 26 failures.

2.i2c_host_stress_all.87117467780503027100881032420906188932646231112292148755052458507051807042847
Line 426, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 7738484645 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2233982

3.i2c_host_stress_all.52121947338353661685884282633855271138118581690676773057309190936481698123915
Line 301, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 20427576899 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @6857552

... and 24 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 32 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 0.i2c_target_stress_all_with_rand_reset.109669519342017929224283966244279430943110977095195173075102911440725614570059
    Line 141, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13661990242 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 0 [0x0])
  UVM_INFO @ 13661990242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_stress_all_with_rand_reset.31911772956904780724846906591286426328273197836253431638133821368132657929232
    Line 93, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 352791609 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 11 [0xb])
  UVM_INFO @ 352791609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_unexp_stop has 30 failures.
  - 2.i2c_target_unexp_stop.3807118279629093977009580662989074881743518370554560733910107922427406680314
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  60462023 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 107 [0x6b])
  UVM_INFO @  60462023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.i2c_target_unexp_stop.27242142872419158400396305843078535863635429851114591890642701705922888518344
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 232522753 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 166 [0xa6])
  UVM_INFO @ 232522753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 28 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
- Test i2c_target_hrst has 24 failures.
  - 1.i2c_target_hrst.107926789751033006431020494196336145480083958129952285141993228639933100418694
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10766375743 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10766375743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_hrst.49963552803491189083065301652895599179922006466760208649348581445468151936748
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10657975422 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10657975422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.16414883160606513051045956810529618904846402767431857941551752775669423459036
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3110161421 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3110161421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.113613494494958340612651759736764186570112497404712357367632717995199959910240
Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2276701587 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2276701587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

1.i2c_target_stress_all_with_rand_reset.75752671646205970751730191021296664340151611728122640505825182068266198075410
Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6373172257 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6373172257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.1686957402488266768875803233364823112372938323738141621489744245205453474849
Line 120, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1808682638 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1808682638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 17 failures:
- Test i2c_target_unexp_stop has 17 failures.
  - 1.i2c_target_unexp_stop.37013793881004540172913185514952022899678115188874055662236919349641779077062
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1798148787 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 1798148787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.i2c_target_unexp_stop.7304292241685518813188538181421081409278909410928343127212492309464826062222
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 302522517 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 302522517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
- Test i2c_target_nack_txstretch has 16 failures.
  - 1.i2c_target_nack_txstretch.105420867326654154889865218424722696730950084561351969380424528689347471512979
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 199477956 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 199477956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_nack_txstretch.65197498519944579686095677103807410480467701840359627346300328578646184846788
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 190739249 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 190739249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 11 failures:

Test i2c_host_mode_toggle has 11 failures.

4.i2c_host_mode_toggle.67286829726364949126262840887386275459954971193903499460099365774221812999518
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 110676798 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

10.i2c_host_mode_toggle.56100189605637414163540133997568136911963918776721827545918351848833626925526
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  50272290 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 9 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 7 failures:

Test i2c_host_stress_all has 7 failures.

0.i2c_host_stress_all.113807290467087801649790218876282226840184945262686269015352162828263948045376
Line 134, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 114205336846 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3024086

4.i2c_host_stress_all.105552259652674296557964089416331397227833532981761961648581376493054478122954
Line 213, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 61637877847 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @21933020

... and 5 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 7 failures:
- Test i2c_target_stretch has 7 failures.
  - 0.i2c_target_stretch.10159950354583012077061659610927222002670028812394268563176960225192846872924
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10007644774 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10007644774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_target_stretch.1328063029716744667525342945068304635982517915929549301473990204194364659652
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10011883966 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10011883966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:

Test i2c_target_unexp_stop has 3 failures.

0.i2c_target_unexp_stop.94189979186788556678268292346760928689296893117247826477072448881666215716416
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 735428625 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 735428625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_unexp_stop.98112642179278015960782111683312865947895088106915226320944026249591948869860
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 449097172 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 449097172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 11.i2c_host_mode_toggle.95577951122821540545530037424315141827486213038151667111822505588092349443361
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  43234211 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x97a87c14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  43234211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.i2c_host_mode_toggle.51368679397494582821594264659200493027888331836547064636264749967102805455735
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 157019737 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xf1f35114, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 157019737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Job timed out after * minutes has 3 failures:
- Test i2c_host_stress_all has 3 failures.
  - 17.i2c_host_stress_all.95825124040268923167882019267953134288503465318614599248156186266572648350283
    Log /nightly/runs/scratch/master/i2c-sim-vcs/17.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 18.i2c_host_stress_all.106979295815405109758799117666988269173863772501756111249363915882824258318960
    Log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 2.i2c_target_stress_all_with_rand_reset.18466453748664845661915826926986116812660759451860582633552757663213707780582
    Line 163, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_host_stress_all has 1 failures.
  - 42.i2c_host_stress_all.41079701618616201415990034122071832166865000483558374311454464929739636127227
    Line 107, in log /nightly/runs/scratch/master/i2c-sim-vcs/42.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:525) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:
- Test i2c_same_csr_outstanding has 2 failures.
  - 2.i2c_same_csr_outstanding.13772203093891481381612308898672255349031583501055428160985051055396891204699
    Line 75, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 120161832 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @ 120161832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.i2c_same_csr_outstanding.6641092955597645001468966736600178147565203973873435542375443540981373143644
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @  19155245 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @  19155245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
- Test i2c_target_fifo_watermarks_tx has 1 failures.
  - 11.i2c_target_fifo_watermarks_tx.18046001290236103210994323309665960054269800706545976883077592781547273834958
    Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
- Test i2c_target_tx_stretch_ctrl has 1 failures.
  - 32.i2c_target_tx_stretch_ctrl.23589682805108926884602563071975104755420428425091425554323296163158489614040
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/32.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 2 failures:
- Test i2c_target_stress_all has 2 failures.
  - 36.i2c_target_stress_all.80846698311431068602900845209278960881903211855962694352821831638355515109980
    Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/36.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 40374813542 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 40374813542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 43.i2c_target_stress_all.71114089207998355286504718769315472573951006755509723141483803761759773547949
    Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/43.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 46519498681 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 46519498681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 26.i2c_host_stress_all.57754204297567856251933266731282168230669952156270256239686341272750110768650
    Line 101, in log /nightly/runs/scratch/master/i2c-sim-vcs/26.i2c_host_stress_all/latest/run.log
```
  UVM_ERROR @ 11929655773 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
  --> EXP:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 41.i2c_host_mode_toggle.24978089416988628375604159299659048113158066149711179086614060571445700459949
    Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/41.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```