KEYMGR Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	37.460s	8.682ms	50	50	100.00
V1	random	keymgr_random	32.130s	4.780ms	49	50	98.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.740s	116.054us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.640s	29.591us	17	20	85.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.990s	559.926us	3	5	60.00
V1	csr_aliasing	keymgr_csr_aliasing	8.100s	365.932us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.190s	155.550us	13	20	65.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.640s	29.591us	17	20	85.00
		keymgr_csr_aliasing	8.100s	365.932us	5	5	100.00
V1		TOTAL			142	155	91.61
V2	cfgen_during_op	keymgr_cfg_regwen	1.555m	17.914ms	48	50	96.00
V2	sideload	keymgr_sideload	22.830s	3.578ms	50	50	100.00
		keymgr_sideload_kmac	28.010s	1.654ms	50	50	100.00
		keymgr_sideload_aes	33.430s	4.612ms	50	50	100.00
		keymgr_sideload_otbn	45.930s	14.082ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	21.030s	758.788us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	15.220s	370.900us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.910s	771.983us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	41.380s	7.810ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	20.310s	1.023ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	17.160s	4.093ms	49	50	98.00
V2	stress_all	keymgr_stress_all	3.829m	10.557ms	50	50	100.00
V2	intr_test	keymgr_intr_test	2.270s	12.848us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.970s	14.569us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.710s	609.076us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.710s	609.076us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.740s	116.054us	5	5	100.00
		keymgr_csr_rw	2.640s	29.591us	17	20	85.00
		keymgr_csr_aliasing	8.100s	365.932us	5	5	100.00
		keymgr_same_csr_outstanding	3.780s	127.691us	13	20	65.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.740s	116.054us	5	5	100.00
		keymgr_csr_rw	2.640s	29.591us	17	20	85.00
		keymgr_csr_aliasing	8.100s	365.932us	5	5	100.00
		keymgr_same_csr_outstanding	3.780s	127.691us	13	20	65.00
V2		TOTAL			728	740	98.38
V2S	sec_cm_additional_check	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
		keymgr_tl_intg_err	7.460s	215.367us	14	20	70.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.440s	733.583us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.440s	733.583us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.440s	733.583us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.440s	733.583us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	11.190s	1.923ms	13	20	65.00
V2S	prim_count_check	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.460s	215.367us	14	20	70.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.440s	733.583us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.555m	17.914ms	48	50	96.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	32.130s	4.780ms	49	50	98.00
		keymgr_csr_rw	2.640s	29.591us	17	20	85.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	32.130s	4.780ms	49	50	98.00
		keymgr_csr_rw	2.640s	29.591us	17	20	85.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	32.130s	4.780ms	49	50	98.00
		keymgr_csr_rw	2.640s	29.591us	17	20	85.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	15.220s	370.900us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	20.310s	1.023ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	20.310s	1.023ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	32.130s	4.780ms	49	50	98.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	23.110s	1.343ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	26.990s	1.152ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	15.220s	370.900us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	26.990s	1.152ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	26.990s	1.152ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	26.990s	1.152ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	19.560s	1.068ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	26.990s	1.152ms	50	50	100.00
V2S		TOTAL			152	165	92.12
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	24.100s	4.476ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1053	1110	94.86

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.13	98.11	98.56	100.00	99.01	98.63	91.11

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 32 failures:

Test keymgr_csr_mem_rw_with_rand_reset has 7 failures.

0.keymgr_csr_mem_rw_with_rand_reset.38095608974244175575228233642780442779647958421779697013544362106274577258582
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @  16857039 ps: (keymgr_csr_assert_fpv.sv:460) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @  16857039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_csr_mem_rw_with_rand_reset.58467685059473324827031392052028554883485602903416413043615268751743748118248
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @  53710137 ps: (keymgr_csr_assert_fpv.sv:460) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @  53710137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test keymgr_tl_intg_err has 6 failures.

2.keymgr_tl_intg_err.26271894816451597233603269366002608731877905685237303010854574508676035224773
Line 97, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @  65657649 ps: (keymgr_csr_assert_fpv.sv:460) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @  65657649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.keymgr_tl_intg_err.40660926733021082640002321083589765700879237592468269559520479307285560900388
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @  87720869 ps: (keymgr_csr_assert_fpv.sv:478) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @  87720869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_bit_bash has 2 failures.

2.keymgr_csr_bit_bash.19189135710721166895220085389917090658097434997167316793849629980224745218742
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @ 1474718544 ps: (keymgr_csr_assert_fpv.sv:490) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @ 1474718544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_csr_bit_bash.11322217049601761185692550206173947806074757529393650829118547875009473443236
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @ 559925531 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @ 559925531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_same_csr_outstanding has 7 failures.

2.keymgr_same_csr_outstanding.90225934244542027605334697218324513185189797498955518775437698722160333866863
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @  89183069 ps: (keymgr_csr_assert_fpv.sv:448) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @  89183069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_same_csr_outstanding.36630517780075827771113142753010963985680698190160058364447647757835940824332
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @  32957587 ps: (keymgr_csr_assert_fpv.sv:484) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @  32957587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test keymgr_shadow_reg_errors_with_csr_rw has 7 failures.

4.keymgr_shadow_reg_errors_with_csr_rw.32361240915658514470054560156995019090619790052120886179321039130010321120082
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @  50065779 ps: (keymgr_csr_assert_fpv.sv:460) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @  50065779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.keymgr_shadow_reg_errors_with_csr_rw.19685214885837188019912793304261460194090317303901216969160993817855120918885
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  93551928 ps: (keymgr_csr_assert_fpv.sv:412) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  93551928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

... and 1 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 2.keymgr_stress_all_with_rand_reset.53935954576174361478257811183277000393214682601658572849059228926409050063236
    Line 1254, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7284408786 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7284408786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.50449413951359230148939362557601620813086828335539204017113995385463758165217
    Line 148, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 406785026 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 406785026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_random has 1 failures.

2.keymgr_random.62505092095949244376798468146412695953565289858840379941663455434750133048049
Line 133, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_random/latest/run.log

  UVM_ERROR @   4536737 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   4536737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_kmac_rsp_err has 1 failures.

15.keymgr_kmac_rsp_err.21612847748607699643470533819690235732938882620360046877692711104163749817975
Line 128, in log /nightly/runs/scratch/master/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  82947533 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  82947533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_otbn has 1 failures.

30.keymgr_sideload_otbn.24332857418463153268083401737201204409319536245185064143809934022827794072709
Line 92, in log /nightly/runs/scratch/master/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest/run.log

  UVM_ERROR @  11203466 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  11203466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_cfg_regwen has 1 failures.

44.keymgr_cfg_regwen.33934833355903403297701346114014262013318706489904220304356584881348213934412
Line 822, in log /nightly/runs/scratch/master/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @ 134945778 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 134945778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 12.keymgr_cfg_regwen.85356934415362769915302631475052236918732813073529605533109549568578101456515
    Line 260, in log /nightly/runs/scratch/master/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @ 197506985 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @ 197506985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 47.keymgr_sync_async_fault_cross.63848091089593992158948187630062887054577258344369605158400009079716971577602
    Line 122, in log /nightly/runs/scratch/master/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  62752007 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  62752007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```