KEYMGR_DPE Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: 2995ba4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	3.275m	36.576ms	49	50	98.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	2.570s	71.102us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	2.480s	33.969us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	13.860s	2.854ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	5.480s	799.965us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	3.220s	99.936us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	2.480s	33.969us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.480s	799.965us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	intr_test	keymgr_dpe_intr_test	2.350s	14.985us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	2.660s	23.099us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	5.350s	453.817us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	5.350s	453.817us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	2.570s	71.102us	5	5	100.00
		keymgr_dpe_csr_rw	2.480s	33.969us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.480s	799.965us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	4.040s	341.610us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	2.570s	71.102us	5	5	100.00
		keymgr_dpe_csr_rw	2.480s	33.969us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.480s	799.965us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	4.040s	341.610us	20	20	100.00
V2		TOTAL			140	140	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	16.570s	1.373ms	5	5	100.00
		keymgr_dpe_tl_intg_err	7.630s	320.058us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	4.880s	182.534us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	4.880s	182.534us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	4.880s	182.534us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	4.880s	182.534us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	7.850s	872.811us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	16.570s	1.373ms	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	16.570s	1.373ms	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			309	310	99.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.07	97.63	90.53	63.14	76.92	94.89	98.57	17.78

Failure Buckets

• UVM_ERROR (keymgr_dpe_scoreboard.sv:565) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 1 failures:
  • Test keymgr_dpe_smoke has 1 failures.

    • 12.keymgr_dpe_smoke.47644711783773307227559636544931914508166507364203919119531506781603022179993
      Line 2508, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/12.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 23375170699 ps: (keymgr_dpe_scoreboard.sv:565) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'hbe94142c4c4ef4adda45f71d0d76c515a2477c766c0c37a6a065a8411ede3849528c4f3284fca3bed053539d35bfb5552fae64b5e3b4321e85972f328806a381 vs. act 'h0
        UVM_INFO @ 23375170699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---