KMAC/MASKED Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.672m	14.132ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.090s	15.679us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.360s	135.961us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.850s	11.984ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.290s	802.561us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.370s	208.338us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.360s	135.961us	20	20	100.00
		kmac_csr_aliasing	7.290s	802.561us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.180s	40.463us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.480s	69.368us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.511m	92.770ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.301m	37.482ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.808m	827.869ms	5	5	100.00
		kmac_test_vectors_sha3_256	33.831m	247.756ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.162m	94.783ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.072m	95.282ms	5	5	100.00
		kmac_test_vectors_shake_128	43.580m	79.530ms	5	5	100.00
		kmac_test_vectors_shake_256	27.686m	58.220ms	5	5	100.00
		kmac_test_vectors_kmac	4.950s	111.759us	5	5	100.00
		kmac_test_vectors_kmac_xof	5.010s	103.291us	4	5	80.00
V2	sideload	kmac_sideload	8.347m	6.501ms	50	50	100.00
V2	app	kmac_app	6.512m	16.173ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.913m	21.546ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.546m	103.669ms	50	50	100.00
V2	error	kmac_error	9.500m	61.918ms	49	50	98.00
V2	key_error	kmac_key_error	20.860s	7.195ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.710s	330.013us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	43.890s	723.463us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	16.800s	723.911us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.477m	27.146ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	42.810s	3.461ms	50	50	100.00
V2	stress_all	kmac_stress_all	39.972m	169.602ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.060s	15.937us	50	50	100.00
V2	alert_test	kmac_alert_test	2.320s	19.714us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.990s	1.241ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.990s	1.241ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.090s	15.679us	5	5	100.00
		kmac_csr_rw	2.360s	135.961us	20	20	100.00
		kmac_csr_aliasing	7.290s	802.561us	5	5	100.00
		kmac_same_csr_outstanding	3.790s	436.796us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.090s	15.679us	5	5	100.00
		kmac_csr_rw	2.360s	135.961us	20	20	100.00
		kmac_csr_aliasing	7.290s	802.561us	5	5	100.00
		kmac_same_csr_outstanding	3.790s	436.796us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.880s	80.609us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.880s	80.609us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.880s	80.609us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.880s	80.609us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.520s	359.561us	14	20	70.00
V2S	tl_intg_err	kmac_sec_cm	1.534m	7.212ms	5	5	100.00
		kmac_tl_intg_err	4.580s	300.101us	14	20	70.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.580s	300.101us	14	20	70.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	42.810s	3.461ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.672m	14.132ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.347m	6.501ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.880s	80.609us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.534m	7.212ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.534m	7.212ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.534m	7.212ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.672m	14.132ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	42.810s	3.461ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.534m	7.212ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.459m	31.869ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.672m	14.132ms	50	50	100.00
V2S		TOTAL			63	75	84.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	6.554m	22.674ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			917	940	97.55

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.12	99.07	94.43	99.89	78.17	97.03	99.38	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_tl_intg_err has 6 failures.

0.kmac_tl_intg_err.2936472030752051485025329876804944179434873835637571657122564903900469525972
Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  23952702 ps: (kmac_csr_assert_fpv.sv:500) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  23952702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_tl_intg_err.30864296789474118515549059443431710114260660736376231174086277651117419624110
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  54301784 ps: (kmac_csr_assert_fpv.sv:536) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  54301784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 6 failures.

3.kmac_shadow_reg_errors_with_csr_rw.63665272885287426737718732173629525905944380038909882447955670388803170275922
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
  UVM_ERROR @  14320313 ps: (kmac_csr_assert_fpv.sv:518) [ASSERT FAILED] prefix_3_rd_A
  UVM_INFO @  14320313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_shadow_reg_errors_with_csr_rw.79645411303592499230309765832503809435542529654142723470237306389539497427453
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @ 133293198 ps: (kmac_csr_assert_fpv.sv:536) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @ 133293198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 0.kmac_stress_all_with_rand_reset.39853425132750924255797008640491035401949729865185276550896626751807064289168
    Line 319, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44104971639 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 44104971639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.kmac_stress_all_with_rand_reset.90166232996856859244620162070444255517083430052340176883085639835034135437280
    Line 254, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16566003609 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 16566003609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_kmac_xof has 1 failures.
  - 3.kmac_test_vectors_kmac_xof.76325836805608819350002116784601460917204868404455937829783614593989367330946
    Line 73, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest/run.log
```
  UVM_ERROR @  80220778 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  80220778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 4.kmac_stress_all_with_rand_reset.42942864517913184968062248469869835135686679312321619074669341934920021647561
    Line 165, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28685690746 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28685690746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 14.kmac_error.55681349132017159651251430255000685156082824732286970944521642294010690113689
    Line 200, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/14.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```