KMAC/UNMASKED Simulation Results

Friday June 06 2025 17:32:35 UTC

GitHub Revision: `2995ba4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.060m	19.619ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.560s	28.545us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.650s	30.745us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.410s	17.800ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.880s	786.650us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.990s	153.144us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.650s	30.745us	20	20	100.00
		kmac_csr_aliasing	8.880s	786.650us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.210s	21.763us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.050s	41.824us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	43.895m	917.096ms	50	50	100.00
V2	burst_write	kmac_burst_write	14.202m	141.237ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.960m	97.282ms	5	5	100.00
		kmac_test_vectors_sha3_256	18.854m	17.345ms	5	5	100.00
		kmac_test_vectors_sha3_384	24.696m	138.973ms	5	5	100.00
		kmac_test_vectors_sha3_512	14.240m	32.462ms	5	5	100.00
		kmac_test_vectors_shake_128	31.855m	378.091ms	5	5	100.00
		kmac_test_vectors_shake_256	27.212m	62.558ms	5	5	100.00
		kmac_test_vectors_kmac	3.810s	112.736us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.560s	228.562us	5	5	100.00
V2	sideload	kmac_sideload	6.317m	17.104ms	50	50	100.00
V2	app	kmac_app	5.121m	157.656ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.236m	17.744ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.019m	38.955ms	50	50	100.00
V2	error	kmac_error	7.756m	57.513ms	50	50	100.00
V2	key_error	kmac_key_error	18.350s	22.934ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.220m	10.042ms	37	50	74.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.640s	1.410ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.140s	1.741ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.163m	16.613ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	38.680s	2.480ms	50	50	100.00
V2	stress_all	kmac_stress_all	32.352m	267.724ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.280s	102.270us	50	50	100.00
V2	alert_test	kmac_alert_test	2.380s	35.512us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.110s	179.625us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.110s	179.625us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.560s	28.545us	5	5	100.00
		kmac_csr_rw	2.650s	30.745us	20	20	100.00
		kmac_csr_aliasing	8.880s	786.650us	5	5	100.00
		kmac_same_csr_outstanding	3.610s	361.655us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.560s	28.545us	5	5	100.00
		kmac_csr_rw	2.650s	30.745us	20	20	100.00
		kmac_csr_aliasing	8.880s	786.650us	5	5	100.00
		kmac_same_csr_outstanding	3.610s	361.655us	20	20	100.00
V2		TOTAL			727	740	98.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.620s	697.249us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.620s	697.249us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.620s	697.249us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.620s	697.249us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.790s	700.784us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	1.091m	21.892ms	5	5	100.00
		kmac_tl_intg_err	6.070s	391.048us	13	20	65.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.070s	391.048us	13	20	65.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	38.680s	2.480ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.060m	19.619ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.317m	17.104ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.620s	697.249us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.091m	21.892ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.091m	21.892ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.091m	21.892ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.060m	19.619ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	38.680s	2.480ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.091m	21.892ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.439m	11.151ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.060m	19.619ms	50	50	100.00
V2S		TOTAL			61	75	81.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.757m	93.218ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			908	940	96.60

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.67	97.23	94.42	100.00	72.73	95.98	99.35	95.98

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 14 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

1.kmac_shadow_reg_errors_with_csr_rw.34286255092097696297798475908289635666739099371642365148850843056979584911260
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  63717529 ps: (kmac_csr_assert_fpv.sv:494) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  63717529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_shadow_reg_errors_with_csr_rw.104501803416900864730531622930519053923871234876866363454392146395427189010155
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @ 261199775 ps: (kmac_csr_assert_fpv.sv:494) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @ 261199775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_tl_intg_err has 7 failures.

3.kmac_tl_intg_err.111035444257833624894480475033221555411452705052991234913161049931928559623520
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  13267755 ps: (kmac_csr_assert_fpv.sv:548) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  13267755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_tl_intg_err.3762972691070060070503352551571518981187952100835283140950675131664091395505
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @  32276764 ps: (kmac_csr_assert_fpv.sv:530) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @  32276764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 2.kmac_stress_all_with_rand_reset.4729102703405171174039081588040651322626471985107401927514557370161390739676
    Line 139, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3347099518 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3347099518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.kmac_stress_all_with_rand_reset.2818255804305142792478995515614081519176530261570783377613249771832648978255
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  24094472 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @  24094472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 7.kmac_sideload_invalid.1006525363229599749573240961030539399221185607737015583496598316981072571298
    Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10489415682 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x98196000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10489415682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 40.kmac_sideload_invalid.49390205970637878006954028780565080561727789499104549891992846460844058576675
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/40.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10109953066 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbdaa6000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10109953066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:

Test kmac_sideload_invalid has 2 failures.

3.kmac_sideload_invalid.48678992322425447352382057215672258832917241291412676941021940752493958884284
Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10090982410 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3ac81000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10090982410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_sideload_invalid.36449482727129555632966675484666084332410439516319260779035808385549811860544
Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10208892242 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x635d3000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10208892242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:

Test kmac_sideload_invalid has 2 failures.

29.kmac_sideload_invalid.46539403320154726153657309219419475002645745439924703824298337650832339936634
Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10074098681 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x1b463000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10074098681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.kmac_sideload_invalid.13863608247213161910448364156293681630146091363695629903894250621185214007321
Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/42.kmac_sideload_invalid/latest/run.log

  UVM_FATAL @ 10090350282 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc260b000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10090350282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 13.kmac_sideload_invalid.9756028261566985563406278639810627437897363171977614293136727222914128307195
    Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10296875577 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa817b000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10296875577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 17.kmac_sideload_invalid.110302701720497689689401373698562993218136519155633419620007931200997572855898
    Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10068850821 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x38a15000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
  UVM_INFO @ 10068850821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 19.kmac_sideload_invalid.28282666157489741386631353884653551886589322193480599698083435164323092285547
    Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10049930465 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x88937000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10049930465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 25.kmac_sideload_invalid.95228957396265159825791444157848007866204865760626323573166682456719482142680
    Line 89, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10145573239 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xafa25000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
  UVM_INFO @ 10145573239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 46.kmac_sideload_invalid.104435021222450681981990839699679912434028438782440935075193712300173381345161
    Line 95, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/46.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10239591293 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4e615000, Comparison=CompareOpEq, exp_data=0x1, call_count=20)
  UVM_INFO @ 10239591293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 47.kmac_sideload_invalid.15477020292553853332772813943658047620820048839200061257356192530037635605433
    Line 95, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/47.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10165274387 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5b280000, Comparison=CompareOpEq, exp_data=0x1, call_count=23)
  UVM_INFO @ 10165274387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```